# FATAL ERROR while loading design # Error loading design

Dear all

i am a new to VHDL and i have to questions

1- iam using model sim students edition to compile the following code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY latch IS
PORT( d,clk: IN bit;
q,nq : OUT bit);

END ENTITY latch ;

ARCHITECTURE behav OF latch IS
BEGIN
p1 : PROCESS (d,clk) IS
BEGIN
IF CLK = '1' THEN
q<=d; nq<= NOT(d);
END IF ;

END PROCESS p1 ;

END ARCHITECTURE behav ;


the compilation pass successful and when i tried to simulate the following errors appears

# ** Fatal: (vsim-3369) Top-level design unit 'latch' specified more than once.
# Time: 0 ns Iteration: 0 Root: / File: NOFILE
# FATAL ERROR while loading design
# Error loading design

Second question

why should i use xinix or altera tools to compile my code and link them to modelsim instead of compiling and simulating on modelsim

Thanks

I suggest not calling your design "latch". These primitives probably already exist.

And why have you called the input "clk" when it is clearly not a clock but an enable?

i changed tge word latch and clk became en and i got the same error !

did you resolve this problem?

I compiled the original version of your code in Modelsim and it compiles without issue and the simulation loads without issue too.

Do you have a testbench you are using? I suspect you have a problem there.