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  1. #1
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    MGT Data syncronization, Length matching between lanes questions

    Can someone Answer following questions:

    1. How does multi lane Xilinx multi-giga bit transceivers (MGT) assemble data from each lane to make a parallel data value? (lets say interface is x8 which has 8 transmit and 8 receive differential pairs)
    2. If each channel/lane in multi lane MGT interface recovers its clock from its own lane then does'nt it mean we do not need any length macthing between multiple lanes?
    3. In PCIe interface the multiple lanes do not needs to be length matched, does this is valid for all other multi-giga bit interfaces other than PCIe?

    Last edited by asimlink; 28th December 2012 at 14:14.

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  2. #2
    Advanced Member level 3
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    Re: MGT Data syncronization, Length matching between lanes questions

    1.) This is protocol dependent. The most common method is to include sync words into the encoded data. The first step in data recovery is to align the serial bits to word boundaries. This is different based on 8b/10b coding or 64b/66b coding. Assuming the word alignment has been found, the "bonding" can occur. In many protocols, special bond symbols are sent from the transmitter at the same time. These arrive at different times at the receiver (and after the CDR and word alignment). The data is placed into a fifo. When the channel bond symbols arrive, the fifo pointers are modified. This allows for word alignment across lanes. The fifo is also used for a related "clock correction" function, where special clock-correction symbols are added. these symbols are either dropped or added twice to the fifo, based on the fifo sizes. This allows the Tx clock and Rx clock to be different -- eg low cost crystal osciallators.

    2.) No, the reasoning is incorrect, though the result is correct. The channel bonding symbols and associated circuits are what allow the channel bonding. The clock recovery is required, but does not factor into this process. For example, the FPGAs also have serdes blocks that can deserialize and delay data on other pins. It is possible to adjust the delay of each IO to center the sampling point within the data eye. This does not mean that each bit will be aligned to the other bits in the bus -- it only means the bits will be received correctly on that IO.

    3.) Multi-lane interfaces will provide some form of bonding mechanism. Not all use bonding characters, but most do. Others may have a skew lane, while others may use a training sequence to do initial alignment. The fifo size affects the maximum skew allowed.

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