casiocalcs
Newbie level 4
Hi, This is my first post!
I am really new to the world of FPGA and am trying to educate myself from a FPGA prototyping textbook, but came unstuck with one of the early experiments.
The Verilog program is a 2-to-4 binary decoder. The UCF is below. I added the "indicator" signal because I was trying to determine if the enable button is working in hardware.
When the program is loaded to the FPGA, I get no LEDs (LED0-LED3) whatsoever ( I do have the normal power, USB and system LEDs).
I presume that there is a design flaw in my code or UCF. Any constructive advice would be greatly appreciated.
-------------------------------------
I am really new to the world of FPGA and am trying to educate myself from a FPGA prototyping textbook, but came unstuck with one of the early experiments.
The Verilog program is a 2-to-4 binary decoder. The UCF is below. I added the "indicator" signal because I was trying to determine if the enable button is working in hardware.
When the program is loaded to the FPGA, I get no LEDs (LED0-LED3) whatsoever ( I do have the normal power, USB and system LEDs).
I presume that there is a design flaw in my code or UCF. Any constructive advice would be greatly appreciated.
Code:
[syntax=verilog]
module two_2_four(
input [1:0] in2,
input enable,
output [3:0] out2,
output indicator
);
//internal signals
wire d0,d1,d2,d3;
wire [3:0] enab;
//body
assign out2 = enab & {d3, d2, d1, d0};
//product terms
assign d0 = (~in2[1] & ~in2[0]);
assign d1 = (~in2[1] & in2[0]);
assign d2 = (in2[1] & ~in2[0]);
assign d3 = (in2[1] & in2[0]);
//misc
assign enab = {enable, enable, enable, enable};
assign indicator = enable;
endmodule
[/syntax]
Code:
[syntax=verilog]
# Slide switches
NET "in2<0>" LOC = "L13"; #SW0
NET "in2<1>" LOC = "L14"; #SW1
#From Starter-3E user guide
NET "enable" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ; # Btn West
# LEDs
NET "indicator" LOC = "F9"; #LED7
#Format from Starter-3E user guide
NET "out2<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; #LED3
NET "out2<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; #LED2
NET "out2<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; #LED1
NET "out2<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = ;8 #LED0
[/syntax]
