Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Setup Time of pulse triggered flip flop Maser/slave or SR flip flop

Status
Not open for further replies.

naavid

Newbie level 6
Joined
Dec 22, 2012
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,348
what is the minimmum setup time of a pulse triggered flip flop such as a master/slave JK or SR flip flop??
 

That really depends on the manufacturing technology of your FPGA/ASIC.
Generally, the tinier the size the lower the time (this is because of the lower parasitic capacitance of the transistors)...
What device are you using ?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top