Instantiation problem

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TOP_dpimref_ROM is
      Port (
		mclk 	   : in std_logic;
      EppDB	   : inout std_logic_vector(7 downto 0);		-- port data bus
      EppAstb 	: in std_logic;								-- Address strobe
      EppDstb 	: in std_logic;								-- Data strobe
      EppWr 	: in std_logic;								-- Port write signal
      EppWait  : out std_logic		
		);
end TOP_dpimref_ROM;

architecture Behavioral of TOP_dpimref_ROM is


component dpimref is
    Port (
		mclk 	   : in std_logic;
      EppDB	   : inout std_logic_vector(7 downto 0);		-- port data bus
      EppAstb 	: in std_logic;								-- Address strobe
      EppDstb 	: in std_logic;								-- Data strobe
      EppWr 	: in std_logic;								-- Port write signal
      EppWait  : out std_logic;								-- Port wait signal
		data      : out std_logic_vector(7 downto 0);
		addr 	   : out std_logic_vector(3 downto 0);
		ROM_wr   : out std_logic
	);
end component;
	
component ram_sp_ar_aw is
    generic (
        DATA_WIDTH :integer := 8;
        ADDR_WIDTH :integer := 4
    );
    port (
        address :in    std_logic_vector (ADDR_WIDTH-1 downto 0);  -- address Input
        data    :inout std_logic_vector (DATA_WIDTH-1 downto 0);  -- data bi-directional
        we      :in    std_logic                                  -- Write Enable/Read Enable
 );
end component;

signal tmpWr : std_logic;
signal tmpData :std_logic_vector(7 downto 0);
signal tmpAddr :std_logic_vector(3 downto 0);
 

begin
Inst_dpimref : dpimref port map(
      mclk     =>  mclk,	    
      EppDB    =>  EppDB,	    
      EppAstb  =>	 EppAstb,
      EppDstb 	=>  EppDstb, 
      EppWr 	=>  EppWr,
      EppWait  =>  EppWait,
		data     =>  tmpData,
		addr 	   =>  tmpAddr,
		ROM_wr   =>  tmpWr
	);
	
Inst_ram_sp_ar_aw : ram_sp_ar_aw port map(
   	 address => tmpAddr, 
       data    => tmpData, 
       we      => tmpWr
);
end Behavioral;

component dpimref is
     Port (
		mclk 	   : in std_logic;
      EppDB	   : inout std_logic_vector(7 downto 0);		-- port data bus
      EppAstb 	: in std_logic;								-- Address strobe
      EppDstb 	: in std_logic;								-- Data strobe
      EppWr 	: in std_logic;								-- Port write signal
      EppWait  : out std_logic;								-- Port wait signal
	   data     : inout std_logic_vector(7 downto 0);
		address 	   : out std_logic_vector(3 downto 0);
		Swrite : out std_logic
	);
end component;

component ram_sp_ar_aw is
     generic (
        DATA_WIDTH :integer := 8;
        ADDR_WIDTH :integer := 4
    );
    port (
        address :in    std_logic_vector (ADDR_WIDTH-1 downto 0);  -- address Input
        data_mem    :inout std_logic_vector (DATA_WIDTH-1 downto 0);  -- data bi-directional
        we      :in    std_logic                                 -- Write Enable/Read Enable
    );
end component;

signal dpimref_reg :std_logic_vector(7 downto 0);
signal mem_reg :std_logic_vector(7 downto 0);

data <= mem_reg when ( tmpWr = '0') else (others=>'Z');
data_mem <= dpimref_reg when ( tmpWr = '0') else (others=>'Z');