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About Matching Network Design

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Ruritania

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How to design the input/output matching network?

Do I need to concern about the output matching status while designing input matching network? and concern about the input matching status while designing output matching network?

Does these two conditions conflict? How to make then both matched?

PS: I thought it was ez at first, but I found it was not so ez while I've been doing this, sigh. I'm now designing a board for a receiver chip, which need to design the I/O matching network out of chip. I first measured the S11 and S22 of the LNA(inside chip), and then calculated the matching network (either T type or Π type). After put the L, C on the board, I measured the S11, S22 again, but it did not work at all. I repeated this many times, so frustrating ... :(

Anyone help me, pls, thank you in advance.
 

these two conditions conflict is just the fact.
SO just in approximately,we separate to design the input and out put match circuit.

after this course design is done,you can use EDA tool to do the the fine design.


In narrow band use,the L type will be enough.
 

There can be also some mistake in the measurements you are doing.
Take real care with the measuerements.
Be sure that the calibration you are doing is all right, etc...
Could you explain how your measurements were performed (with and without matching network)?
S.
 

i think the frequency of operation is a factoe also
then u have to use transmission line matching network insted of lumped element matching network

also check the self resonsnce frequency of the capacitors and inductors u use
 

Thank you all for the reply.

The following is something I forgot to mention last time:

1. The operating freq. of the receiver is 433.92MHz, which is in the ISM band.

2. The procedure I performed the measurement:
(1). I first designed a PCB board with metal runners as short as I can (I assumed that the freq. is not so high, so I used short metal runners to neglect the transmission line effect).
(2). I then solder a capacitor as large as 1u to block the DC at both input port and output port, respectively. and then the SMA connector.
(3). With power on, I measured the S11 and S22 (Surely I did it after having calibrated the VNA).
(4). By using ADS, I calculated and designed the matching network for both input and output. The simulated S11 and S22 were both less than -20dB.
(5). Then I soldered the LCs with the values obtained from step 4, with the DC blocking capacitor removed.
(6). Then I repeated step 3. But the result were really bad, it was almost the same with no matching network at all, say, above -1dB.

(In addition, the capacitors and inductors I used are all from Murata.)

Thanks again for your attention, I wish I could get more suggestions.
 

khouly said:
i think the frequency of operation is a factoe also
then u have to use transmission line matching network insted of lumped element matching network

also check the self resonsnce frequency of the capacitors and inductors u use
Click to expand...

How to check the self resonance freq. of the LCs? Is there any good method? I wanted to do this too, but failed.

Thank you.
 

Ruritania said:
Thank you all for the reply.

The following is something I forgot to mention last time:

1. The operating freq. of the receiver is 433.92MHz, which is in the ISM band.

2. The procedure I performed the measurement:
(1). I first designed a PCB board with metal runners as short as I can (I assumed that the freq. is not so high, so I used short metal runners to neglect the transmission line effect).
(2). I then solder a capacitor as large as 1u to block the DC at both input port and output port, respectively. and then the SMA connector.
(3). With power on, I measured the S11 and S22 (Surely I did it after having calibrated the VNA).
(4). By using @DS, I calculated and designed the matching network for both input and output. The simulated S11 and S22 were both less than -20dB.
(5). Then I soldered the LCs with the values obtained from step 4, with the DC blocking capacitor removed.
(6). Then I repeated step 3. But the result were really bad, it was almost the same with no matching network at all, say, above -1dB.

(In addition, the capacitors and inductors I used are all from Murata.)

Thanks again for your attention, I wish I could get more suggestions.
Click to expand...

Dear Ruritania

The poor VSWR in your step(6) is an ordinary result. because you do not consider S21 and S12 parameters.

The device is not unilateral, so the input impedance of TR in your step(6) might differ from the measured one in step (3), because the output termination impedance differs each other. (50-ohm terminnation in step(3) and inserted matching network in step(6) )

If you want to acheive simultaneous input-output matching,
refer to below procedure.
1. you have to use all S-parameter of TR(S11/21/12/22)
2. Calculate stability factor K of TR(refer to "Microwave Engineering", David Pozar)
a. If K>1 , the simultaneous input-output matching network can be synthesized.
b. If K<1 , use the series or parallel feedback network to make K less than 1.
then, go to step 2,(a)

PS : Don't forget the de-embedding process when you measure the TR impdeance.
The nonconsidered connectors or PCB-lines may have a bad influence on your work.

BR.
 

Yes, i think the reason is S12 is too large.
By hte way, does it need calculate the delta (make sure that delta<1) when calculate stability factor K?
 

Both delta and K must be taken under consideration, when you check the stability of the design. Only when the two conditions are fulfilled you may be sure, that everything is OK

Best regards
ania
 

if you have ADS, it will be a very easy thing.
there are smith tool in the ADS, the simple match they can do.
there are match controller in the ADS, they can do it.
 

Thank you all for the suggestions. They did help me a lot.

I made some progress, I've got an S11 less than -20dB. However, it is still very very hard to make both of S11 and S22 match at the same time(say, both less than -15dB).

And one thing I wanna mention here is that, the measurement results always greatly differ from the simulation results, sometimes even the tendency cannot agree with each other.

One more question here: what is the problem when the mesuring curve goes out of the Smith Chart while using VNA?

Thank you.\]
 

One reason that your simulation is different from the measurement, is because probably you didn’t take in consideration the parasitics.
Usually when the curve goes out of the Smith chart means that your circuit is unstable at some frequencies. Check for oscillations with a Spectrum Analyzer, using a wide span.
 

vfone said:
One reason that your simulation is different from the measurement, is because probably you didn’t take in consideration the parasitics.
Usually when the curve goes out of the Smith chart means that your circuit is unstable at some frequencies. Check for oscillations with a Spectrum Analyzer, using a wide span.
Click to expand...
sorry i have one question how do i know the circuit is oscillation on the Spectrum
i mean what happen will be seen on the Spectrum some spur on it or ....
 

marty,
If is oscillating you will see the spurs on the Spectrum Analyzer (that is connected at the output of your amplifier). These spurs could appear with, or without signal at the input of your amplifier.
Another indicator of unstable amplifier is when S11 is going positive (S11 > 0).
Check in your simulation for K factor, that for a stable amplifier shall be K > 1.
**broken link removed**
 

since it has not been mention yet, you may also use manufacture published S-parameters for L's and C's in your simulation to obtain better accuracy
 

Hello, I think your problem that you ignore the effect of S12,so try to follow the following procedure:
1)calculate the K of the transistor at specified freq., Vce & Ic, if k>1 then your Transistor is unconditionally stable so go through next steps.if not then you have to do another procedure.
2)do the matching using "Simultaneously conjugatlly Matching" method
3)after calculating the Ys,YL from step3,then these valuse should the transistors see at the input/outout ports,so you have now to design a matching circuit (L or π or T matching method) to match the source RS to looks like Ys• , and RL to looks like YL•
4)now you can calculate the values of C,L by using formulas or smith chart.
5)if you follow the above procedure you should the got a gain called Tranceducer Gain,wich it is the actuall gain after donig matching.
note: refer to RF Circuit Design by Bowiks
regards
 

If you can't match both port simutaneously and you see S11 or S22 is going out of the Smith chart on VNA, that means the amplifier's K is less than one at some frequency, it is impossible to match both ports at that frequency.

Curves going out of the Smith chart means that at some frequency you got a negetive resistance. And this implies that the amplifier might turn to be a oscillator if you terminate the ports with improper impedance.
 

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