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    FPGA implementation of a CIC decimation filter for a single-bit sigma-delta modulator

    Dear all,

    I want to design a CIC decimation filter for a 3rd-order sigma-delta modulator with single-bit quantization.*As we know, CIC filter need's 2's complement arithmetic. Let's assume I need 16 bits internal word length for correct operation.

    Now my question is, do I need to convert my 1-bit unsigned quantized data (at the the modulator output) to the equivalent 16-bit 2's complement world length at the input of the CIC filter?

    In other word, do I need to convert 1b'0 to -1 = 16'hFFFF, and 1'b1 to +1 = 16'h0001.

    Thanks for your help.

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    Re: FPGA implementation of a CIC decimation filter for a single-bit sigma-delta modul

    CIC don't particularly need two's complement, because signed/unsigned is only a matter of number interpretation for addition and substraction. You can implement it either with unsigned or signed arithmetic. The data coding can be converted at the output, e.g. from offset binary to two's complement by inverting the MSB.

    In other word, do I need to convert 1b'0 to -1 = 16'hFFFF, and 1'b1 to +1 = 16'h0001
    This way, you would multiply your input bit by two, which is usually unwanted, but possible. Otherwise sign extension at the input is required, giving input codes 0 and all 1.



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    Re: FPGA implementation of a CIC decimation filter for a single-bit sigma-delta modul

    Thanks FvM,

    The reason I said signed number, is that as long as I know we leverage the 2's complement wrap around in integrator sections to avoid overflow problem. I don't know how can we do it with unsigned number.

    Also if we do not convert 0 to -1, there will be no subtraction in integrator sections. because when input is 0, nothing will be added or subtracted.

    Finally I dont understand why you say converting 1b'0 to -1 = 16'hFFFF, and 1'b1 to +1 = 16'h0001, is like multiplying the input bit by two.

    Please correct me if I am wrong.
    Thanks in advance.



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    Re: FPGA implementation of a CIC decimation filter for a single-bit sigma-delta modul

    According to my suggestion, you'll add 0x0000 and 0xFFFF for 0 and 1, or vice versa.

    Both signed and unsigned arithmetic will overflow (modular addition) as required by the CIC design. As said, signed and unsigned adder are just the same on the gate level, only the number interpretation changes.


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