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VHDL SPI code testbench ok but no syntheiszable

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SOMANDAL88

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I am trying to build a SPI interface using VHDL. The testbench is ok. But it is not synthesizable on Spartan 6. Could anyone please figure out the problem.

Code VHDL - [expand]
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LIBRARY IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity L6470_SPI_MASTER is
port(clk: in std_logic;
    sdo_master: out std_logic;
    ck_master: out std_logic;
    cs_bar: out std_logic);
end L6470_SPI_MASTER;
architecture arch of L6470_SPI_MASTER is
signal temp: integer range 0 to 9;
signal reg_array: std_logic_vector(7 downto 0);
begin
process (clk)
variable count: integer range 0 to 10:=0;
begin
if (rising_edge(clk)) then
count :=count+1;
end if;
if (count=10) then
count:=0;
end if;
temp<=count;
end process;
process(temp)
begin
case temp is
when 0 => cs_bar <= '1'; 
when 1 => cs_bar <= '0';
when 2 => cs_bar <= '0';
when 3 => cs_bar <= '0';
when 4 => cs_bar <= '0';
when 5 => cs_bar <= '0';
when 6 => cs_bar <= '0';
when 7 => cs_bar <= '0';
when 8 => cs_bar <= '0';
when 9 => cs_bar <= '0';
end case;
end process;
process (clk)
variable piso_reg: std_logic_vector (7 downto 0):= "11001010";
begin
if (rising_edge(clk) and temp=0) then
reg_array(7 downto 0)<=piso_reg(7 downto 0);
elsif (rising_edge(clk)) then
sdo_master<=reg_array(7);
reg_array(7 downto 1)<= reg_array(6 downto 0);
reg_array(0)<='0';
end if;
end process;
ck_master <= not(clk);
end arch;
 
Last edited by a moderator:

you shouldnt have code outside the clocked part of the process unless it is an async reset. The async reset should have priority over the clock.
 

Do you mean that you want to synthesize a testbench to fit in a Spartan6? By definition a testbench is meant to fit in a device but runs on a simulator (like Modelsim, Active HDL, ...)
 

To lucbra
No, I mean to say that the testbench runs well in VHDL Testbench file in PC. But I was unable to synthesize the code on FPGA.
Actually, I have a L6470 IC which drives high current stepper motor (upto 7 A Vpeak). It works on SPI based commands. I was unable to run it by the code which I presented due to the fact that it was not synthesizable on FPGA Spartan 6. If you have some alternative please suggest like in previous post trickydicky suggested one. Unfortunately it didnt work.
 

Tricky referred to the process starting at line 15
the part where count is checked for a value of 10 should be in the rising_edge part of the process
so something like:

Code VHDL - [expand]
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process (clk, reset)
variable count natural range 0 to 10 := 0;
begin
   if reset = '1' then
      temp <= 0;
   elsif rising_edge(clk)
      if count = 10 then
         count := 0;
      else
         count := count + 1;
      end if;
      temp <= count;
   end if;
end process


second, what's the clock frequency of your SPI_Master module?
 
Last edited:

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