Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Yet another lockup latch question

Status
Not open for further replies.

mhdft

Newbie level 2
Joined
Nov 14, 2012
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,295
I tried to find an answer to my question, but no threads seem to have the complete answer.
So, here is the question:

Assume that we have the following cases:
CLK1+ : Posedge CLK1 scan flop
CLK1- : Negedge CLK1 scan flop
CLK2+ : Posedge CLK2 scan flop
CLK2- : Negedge CLK2 scan flop

Which of the following scan chain connection cases requires a lock-up latch and why?

CLK1+ ---> CLK2+
CLK1+ ---> CLK2-
CLK1- ---> CLK2+
CLK1- ---> CLK2-

Thanks!
 

In test mode, all flops should be clocked by the same clock. Needing lockup or not depends if there is hold time between two flops.
 

Thanks for your response. Yes, CLK1 and CLK2 are irrelevant, I tried to show that there is considerable skew between these clock ports of these flops. The real question is + => - or - => + transitions.
I would think + => - should not need a lockup latch. How about - => + ?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top