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near module syntax error in model sim using d ff

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gkj

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module dff(q, q1,d,d1,clk,reset);
output q,q1;
input d,d1,clk,reset;
reg q,q1;
always@(posedge reset or negedge clk )
begin
if(reset)
begin
q=1'b0;
q1=1'b0;
end
else
begin
q=d;
q1=d1;
end
end
endmodule
this is my code i getting syntax error in first line of in model sim please rectify that
 

I don't get any errors compiling in Modelsim SE 64 10.1b.

I just copied your text into the file dff.v and ran:
vlog dff.v
vsim dff

and it didn't throw any warnings or errors.

Now on the other hand you should use non-blocking assignments in your clocked always block as this represents HW.
If you don't know the difference read the following:
https://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf

Also you should use the C like syntax for the port definitions, so you don't have to keep repeating the port names.

module dff (
output reg q, q1,
input d, d1, clk, reset
);
etc..

Regards,
-alan
 
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    gkj

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Many times when you get an error on what seems like a perfectly fine line of code, it is the line(s) or file before it that is causing the problem. It would really help if you showed the actual error message.
 
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    gkj

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ya sir but i also do that in xilinx iam getting no errors
im doing project on digital pll in 3-10 ghz range .so im using
dff as my phase frequency dectector .one input is clk and other
input is dco clk .i dono how to take the output.please help me sir.

- - - Updated - - -

sorry sir i saved the file as vhd so that only im getting error
thank u

- - - Updated - - -

ya sir but i also do that in xilinx iam getting no errors
im doing project on digital pll in 3-10 ghz range .so im using
dff as my phase frequency dectector .one input is clk and other
input is dco clk .i dono how to take the output.please help me sir.
 

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