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  1. #1
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    the temperature in asic libraries

    I had some questions about how to use the ASIC libraries during synthesis (synopsys).

    I have a fast.db, slow.db and a tpz.db The fast and slow define the cell while the tpz has the pad information and some wire load models. The fast and slow libraries also have wire load models.
    Which wire load models should be selected and how do I use the pad information for my synthesis.

    How do I tell the tool to select the best model it seems fit?

    Is it possible for the tool to mix the fast and slow libraries and choose the fast cells only when required, to fix the slack. I heard that ambit can do this.

    Thanks in advance!!

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  2. #2
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    Re: ASIC libraries

    Quote Originally Posted by peen1
    I had some questions about how to use the ASIC libraries during synthesis (synopsys).

    I have a fast.db, slow.db and a tpz.db The fast and slow define the cell while the tpz has the pad information and some wire load models. The fast and slow libraries also have wire load models.
    Which wire load models should be selected and how do I use the pad information for my synthesis.

    How do I tell the tool to select the best model it seems fit?

    Is it possible for the tool to mix the fast and slow libraries and choose the fast cells only when required, to fix the slack. I heard that ambit can do this.

    Thanks in advance!!
    Hi peen1:

    For synthesys, we normally use the slow lib because we need to fix the slack of

    set-up, and leave the slack of hold to the backend tools.

    wang1



  3. #3
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    Re: ASIC libraries

    Since Pad cells are instatanced directely. The pad ring module is only linked in top level during logic synthesis.



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    ASIC libraries

    1.select slow.db as target library , tpz.db is set as link library;
    2. you can use wire load model in slow.db



  5. #5
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    Re: ASIC libraries

    Quote Originally Posted by peen1
    Which wire load models should be selected and how do I use the pad information for my synthesis.

    How do I tell the tool to select the best model it seems fit?
    The wireload selection depends on the size of the design...
    for eg in tsmc 13u lib

    tsmc_wl10 is used for design of approx 10kgates
    tsmc_wl50 is used for design of approx 50kgates
    ...
    For more accurate results.. u have to genrate a custom wirelaod model for your design with primetime


    Is it possible for the tool to mix the fast and slow libraries and choose the fast cells only when required, to fix the slack. I heard that ambit can do this.
    fast and slow are only operating conditions... however you synthesize the gate which going to be in slicon is the same.... slow library assumes your chip operates in worst conditions like high temperature(125 degree typicaly) and lesser Vdd.

    I heard that ambit can do this.
    if you are talking about Multi Vth design... may be ambit can do...
    though power compiler is the best option


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  6. #6
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    Re: ASIC libraries

    The fast and slow library can be used in Primetime for both case timing analysis.



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  7. #7
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    Re: ASIC libraries

    how about 50k+ gates?



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