H.Hachem
Junior Member level 3
Hi,
I'm designing a CIC filter on an FPGA. I applied the bit pruning algorithm as described in Hagenauer's paper, however it is unclear to me how the gain is affected by such procedure. Normally CIC filters' gain is (RM)^N. However, after truncation the amplitudes cannot reach (RM)^N due to limited bit precision. So how does the gain get affected by bit pruning? Is there any formula?
On the other hand, if I have multiple CIC filters connected to each other, is it better to adjust the gain at the end of each filter or at the end of the whole chain?
P.S. : I adjusted the gain of the first filter by simply dividing the output by a constant, so that low frequencies pass through, while high frequencies get blocked. However, I did that by trial and error, and I'm not sure that applies to all frequencies.
I'm designing a CIC filter on an FPGA. I applied the bit pruning algorithm as described in Hagenauer's paper, however it is unclear to me how the gain is affected by such procedure. Normally CIC filters' gain is (RM)^N. However, after truncation the amplitudes cannot reach (RM)^N due to limited bit precision. So how does the gain get affected by bit pruning? Is there any formula?
On the other hand, if I have multiple CIC filters connected to each other, is it better to adjust the gain at the end of each filter or at the end of the whole chain?
P.S. : I adjusted the gain of the first filter by simply dividing the output by a constant, so that low frequencies pass through, while high frequencies get blocked. However, I did that by trial and error, and I'm not sure that applies to all frequencies.