how can i fix timing violation in i2c simulation result?

Hi~

i have question about opencores i2c slave simulation results.

Q1) how can i use "sda_dly" for fix 0 hold margin?

Q2) how can i fix timing violation in i2c simulation result?

Q3) why happened timing violation

Warning! Timing violation
$setup( posedge scl:742686 NS, negedge sda &&& scl:745866 NS, 4700.00 : 4700 NS );
File: /home/sylee/a/bench/verilog/i2c_slave_model.v, line = 348
Scope: tst_bench_top.i2c_slave
Time: 745866 NS

Warning! Timing violation
$setup( posedge scl:1260846 NS, negedge sda &&& scl:1264026 NS, 4700.00 : 4700 NS );
File: /home/sylee/a/bench/verilog/i2c_slave_model.v, line = 348
Scope: tst_bench_top.i2c_slave
Time: 1264026 NS


and also how can i fix this timing violation? isn't it meet MIN timing t_su,STA 4.7 ?

Q5) why it be Timing violation?

Q6) i can find comment like following as

// generate delayed version of sda
// this model assumes a hold time for sda after the falling edge of scl.
// According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
// with regards to scl. If the data changes coincident with the clock, the
// acknowledge is missed
// Fix by Michael Sosnoski
// assign #1 sda_dly = sda;

so how can i use this ?