hpb
Member level 2
hello,
here is an interesting scenario..
i`ve main design coded in vhdl...
processor bfm in systemverilog...
and a micron memory model in verilog...
Using modelsim Altera 6.6d, how to verify the main design.
what are steps to be followed during instantiation....
waiting for replies.....
here is an interesting scenario..
i`ve main design coded in vhdl...
processor bfm in systemverilog...
and a micron memory model in verilog...
Using modelsim Altera 6.6d, how to verify the main design.
what are steps to be followed during instantiation....
waiting for replies.....