Steps and Precautions for Plane Cutting in Power and Ground layers

Hi,
I am designing a 4 layer High Sampling DAC Board, Since it is a DAC i need to give proper Analog and Digital Grounding, and I have successfully done that in my schematic design, now i am supposed to layout the circuit and i am doing that on a 4 layer board, i need to do plane cutting in Ground and power planes. please suggest me good techniques to do the plane cutting.
I have 4 different grounds and 5 different voltages with proper isolation between each of them through ferrite beads.

Thank You.

For the ground DONT.
4 grounds! Why?
I would reccomend you do some serious research around the web, most people reccomend that you dont split the grounds, but seperate your analogue and digital into to seperate areas to avoid the signals interfering, so you end up with a analogue area and a digital area, but one contigous ground.

www.hottconsultants.com/pdf_files/june2001pcd_mixedsignal.pdf
www.sparkfun.com/datasheets/.../mixed_signal_design.pdf
www.x2y.com/.../TechDay09kr_hpa_Track2_1_Precision_Analog_...

Hi @Marce,
Thank you for those links, i just have some queries w.r.t those links, please try to answer them.
In the first pdf page - 2; explanation about split plane is given, Split Plane has to be avoided and if it is done then the ways suggested to do so are:

1 - Bridge Technique, where both planes are connected and traces are routed over that bridge.
2 - Using optoisolators.
3 - Using Transformers.
4 - Using Differential Traces.

My queries are:

1 - How do we implement Bridge technique physically on board, one thing that i'm doing is connecting those grounds using a 0ohm resistor, what are the other different ways?
2 - I never knew that an optoisolator/transformer can be used in such a way, in fact i have by far not seen any design inculcating such a technique, if these techniques are used then how are they implemented practically on a PCB(since they seem promising theoretically)?

The signal that i'm going to cross over the planes are differential and so i don't have to bother i guess.

4 grounds! Why?

Click to expand...

The IC itself requires 3 grounds as suggested for it by the manufacturer, and i am isolating the rest of the circuitry with the 4th ground.

- - - Updated - - -

One more query in the 3rd page(first Link/pdf):

3 - In the middle paragraph there is bridge technique suggested for split plane, stating

"If you use this approach, you should make the bridge between the two ground planes as wide as the IC"

Click to expand...

Now the way i'm doing it in my board is similar to what is suggested for split planes with bridge technique but i'm not connecting the bridge below the ic, precisely speaking, there is a gap right below the IC between the analog and the digital planes which is the split clearance, now what problems might arise due to this?

Image Here: http://obrazki.elektroda.pl/2884543900_1350973575.jpg

One query on page 4:
The mid Paragraph talks and asserts clearly about the usage of Power plane splitting, and the last but one sentence of the middle paragraph states this:

All traces crossing over the power plane split must be on a layer adjacent to the solid ground plane

Click to expand...

what does this mean?

Please let me know if my questions are unclear.
Thank You

before I answer in more detail, could you let us know what part your using, I'm intreged with the fact it requires 4 grounds.

I'm using an AD9117 and it requires 3 grounds, 1 for analog, 1 for digital and 1 for clock.

I'll be back, I'm holiday so not as active as I usually am.

Ya sure take your time, even I'm doing the layout pretty slowly, so that i can avoid all sorts of potential risks.

Had a look at the data sheets and evaluation board:
https://wiki.analog.com/resources/eval/dpg/eval-ad971x_ad911x
When there is and evaluation board I would use that as a reference for my layout, and if I was doing a layout with this device that is waht I would do.
Splitting grounds is a complex subject hence why so many say dont. On layouts using similar devices what I have done is have the grounds seperate initially, for placement and routing and creating the splits in the grounds. This way I can have the ground areas difeerent colours to make shure I do not cross any splits with any routes and to ensure all routes are over thier respecyive ground areas. Then join the grounds on the main ground layer under the device, usualy the thermal pad to ensure a low impedance connections. Though for for a first issue board we may use zero ohm resistors for development. The reason why we join on the ground layer is we have had problems in the past with EMC testing and split grounds connected by quite high impedance (compared to a plain) zero ohm links.
Splits in power planes have the same effect as a split in the ground planes, signals can use power planes as a return path, if signals do cross and there is no adjacemnt ground plane a bridging capacitor over the split nest to the signal is recomended. As you can imagine this can get painful during layout, so where possible I stick to best practice and bury all critical signals between ground planes, if the design and costs will allow.
As to galvonic isolation, the ADUM series now has versions that will isolate the power, or you can use an isolator and a seperate isolator for the power, again there are dwonsides, the main one being space, it takes up a lot of room.
I slao prefer not to route diff pairs over splits if possible, they are still coupled to the return plane, its just that as the signals are also closely coupled they cancel out the return current.
Have fun.

Thanks marce,

When there is and evaluation board I would use that as a reference for my layout, and if I was doing a layout with this device that is waht I would do.

Click to expand...

Well honestly that is what i am doing and in his layout he has made around 5 or 6 Gnd planes but since my design is a subset of his, i was able to pull this off with 4 Gnds, the very reason that the evaluation board has split grounds has forced me to split my ground.

The reason why we join on the ground layer is we have had problems in the past with EMC testing and split grounds connected by quite high impedance (compared to a plain) zero ohm links.

Click to expand...

Please accentuate more on this.

As to galvonic isolation, the ADUM series now has versions that will isolate the power, or you can use an isolator and a seperate isolator for the power, again there are dwonsides, the main one being space, it takes up a lot of room.

Click to expand...

Sorry i have heard about galvanic isolation but don't know much about it, can you please elaborate.

I slao prefer not to route diff pairs over splits if possible, they are still coupled to the return plane, its just that as the signals are also closely coupled they cancel out the return current.

Click to expand...

Well i have no option with this, i am forced to route 2 differential signals through the split plane, can't help it!.

During EMC testing, and sometimes during operation having a small high impedance link (a zero ohm) resistor between two grounds (or more) can cause one ground to be at a different potential than another, this can casue convertion problems with DACs ADCs, as theoreticaly we want the ground to be at the same potential.
Galvonic Isolation:
https://en.wikipedia.org/wiki/Galvanic_isolation
As to the diff signals if it can be avoided theres no way round it, at least there will be a lot less problems than single ended signals.

Well i think i got this thing, and in fact there is a circuit in my board which i am using to provide isolation below is the image

FIGURE

So i hope the above diagram makes it clear about the 3 grounds in my board, and it also shows how a single input ground is broken down to 3 grounds.

Just have a gander at the circuit and suggest any changes if you have for it.

Thanks.