Hi, this topic was discussed before, it did show 5 threads when i typed the tilte.
here is one https://www.edaboard.com/thread102298.html

i almost used the same CMFB scheme as the last post for the class AB output stage, that is tuning the PMOS gate by adjusting the current into the output nodes. check the picture below
Click image for larger version. 

Name:	Capture.PNG 
Views:	21 
Size:	72.1 KB 
ID:	81313
this works, especaily works good in continous time, but for Swtiched cap version, it doesn't work well, i think due to very low CMFB loop gain (less than 1.5 dB gain in my case) and in turn can cause very low bandwith (1.5MHz), the phase margin is extremly high since is a single pole system.

do you have any ideas or reference regarding this problem, how to do SC-CMFB for Class AB output stage?

Thanks!