Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
What sort of waveform are you dealing with? If all you want is a square wave at the output you can use a PLL operating at twice the frequency an a divide by two that generates the output of your circuit and also is fed to the phase detector.
If your chip has multiple clock domains and you've to reinforce scan chain locking (avoid scan feed through) during scan shift & capture cycles, you my have to define multiple clocks to have non-50% duty cycle and they are triggered at different time within a single test cycle.
One limit of defining duty cycle of test clock is the test clock frequency and the duty cycle limit from the FF used in your cell library.
Usually you can generate a verilog simulation testbench to try running your ATPG patterns with post-layout timing(using Synopsys DFT compiler & TetraMax).
If your chip has multiple clock domains and you've to reinforce scan chain locking (avoid scan feed through) during scan shift & capture cycles, you my have to define multiple clocks to have non-50% duty cycle and they are triggered at different time within a single test cycle.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
