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  1. #1
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    VHDL - Designworks 5 Runtime Error 680

    My code compiles without any errors, but when I try to run the simulation I get "Runtime Error at or near line 59 in process PROCESS000002_56 type PROCESS000002_56". Attached are my device and its testbench. It's the device that prompts the error. My testbench has an empty stimulus process because I'm stuck with the device.

    fp_add.txt
    fp_test.txt

    Can someone tell me what the error means, how I can fix it, and how to avoid the same thing in the future?

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  2. #2
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    Re: VHDL - Designworks 5 Runtime Error 680

    This code does not conform to any standard templates. Did you write the code, or get disgnworks to export it? What simulator are you using? I am not familiar with design works.

    This code probably wont synthesise for an FPGA because of the odd coding stule and the use of internal tristates. But the runtime error points to a variable declaration. Are you sure this is the correct code?



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  3. #3
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    Re: VHDL - Designworks 5 Runtime Error 680

    My partner wrote the code. The simulator is the one that Designworks runs.

    According to my professor, the runtime error is due to the compiler being unable to allocate space. Declaring a dummy variable under the problem line solved it.



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  4. #4
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    Re: VHDL - Designworks 5 Runtime Error 680

    sounds like a buggy compiler to me.



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