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    what tools used in system-level verification

    Hi
    everyone!

    What's popular tools used for system-level verification?

    Thanks !


    zhpy

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    Re: what tools used in system-level verification

    SystemC, SystemVerilog



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    what tools used in system-level verification

    I just use verilog, and think verilog can do every thing.



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    what tools used in system-level verification

    I think if a design is includeing cpu or mcu, should use assembly or c to verify



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    Re: what tools used in system-level verification

    Hi zhangpengyu:

    If you design communication chip, I think vera|e will be a choice for verification.



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    what tools used in system-level verification

    You should use SystemC because of its convenient. In addition, it is an open-source tool.



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    Re: what tools used in system-level verification

    There are various methodologis by which you can do verification some of the tools i am mentioning below -
    a. Specman based or
    b. Micropack based (ARM) or
    c. SystemC (cadence) based or
    d. TCL/TK based or
    e. VHDL/Verilog based or
    f. Combination of the above



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    Re: what tools used in system-level verification

    There are various tools by which you can do verification .
    but i say Specman or System C + perl is very good option,
    traditional verilog based is more or less hardware type, it should not be like that.
    Verification env should be software type.



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    Re: what tools used in system-level verification

    The most popular verification tool which can support system-level is SpecmanElite from Verisity Co. It includes both of low-level and high-level structures to write properties and assertions. The low-level structures includes CTL and LTL. But high-level structures include some structures like class in C++. For example you can describe a CPU based on a structure like class definition in C++ and write lots of properties based on it. Therefore, you can write some high-level descriptions which are neccesary to do system-level verification. In this way, you are able to do equivalence checking, if you describe the system in a high-level of abstraction.

    Regards,
    KH



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    what tools used in system-level verification

    spauls, could you give an explanation of how which kind of tasks will use perl to implement, which kind of tasks will use use systemc to implement?

    how to dynamically generate stimuli with systemc? how to specify a test case with a systemc -based testbench?

    thanks



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    Re: what tools used in system-level verification

    Id depends on the nature of the project. Mostltly system level verifcation invloves Verilog(reused from block level or Full Chip level) , parts of C code ( drivers or the boot up code or other intrerupt related code) developed by Software team or teh foem ware team, Asssembly code ( if a Processor is involved ), pli routines to link up all these. It is not always necessay to have this setup. For the deisgn which has llow software depency ( menas just sretting some regiates or booting up ) pure verilog/C/Specman/Vera can be used. My personl opinion is that SystemC is more used for performance modelling at the SysyemLevel that directly using this for the sysyem levele verifiication



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    Re: what tools used in system-level verification

    C/C++
    If it is related to digital signal processing, SPW/Cossap/Matlab/Simulink can do.



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    what tools used in system-level verification

    There is not a general answer for this question. It depends on the complexity of the job, the resource you may use. of course your habit at the same time.



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    what tools used in system-level verification

    so many different languages and tools can fuzzy me



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    what tools used in system-level verification

    systemc, systemverilog, c, c++



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    what tools used in system-level verification

    u can do one thing make good hand on any one language like verilog,C.and u can do command on any verification language.
    either it
    1.tcl/tk
    2.vera
    3.system c
    4.system verilog
    5.arm



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    Re: what tools used in system-level verification

    It depends what you want to simulate or modelling:

    Digital:
    SystemC, VerilogC

    C/C++

    VHDL/Verilog (Modelsim, LDV)

    Analog:
    Matlab (for very complex systems like receiver with rf frontend, sigma-delta converter, baseband processor)

    C/C++ complex and difficult to read for other designers, but very fast

    AHDL/VHDL-ams
    Good for low complexity of the analog part, good for integration with digital system

    Saber



    Mixed Signal

    a combination of the tools described above, in most cases slow due ot the performance loos of the simulator[/b]



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