Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

question on esd diode damage

Status
Not open for further replies.

mohdfaaf

Junior Member level 2
Joined
Sep 26, 2004
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
malaysia
Activity points
259
Need any input/suggestion on this:
It is found that on some I/O pins the esd margin has significantly degraded on CDM testing. Failure analysis showed the diode ( in the esd basic cell ), was damaged. The mystery lies in this damage only affects certain I/O pins not others. And other i/o pin actually has the same esd cell used. ( same circuit block - but layout wise not confirmed the same yet to this time )

Any input or suggestion on finding the root cause is greatly appreciated.
 

CDM ESD assumes the part is charged and the ESD discharges the part through the pin under test. Do the pins being damaged have more capacitance on them. This would allow more charge to be stored and cause a higher peak current and a longer discharge pulse.

The only impedence in the discharge path for CDM is the parasitic impedence of the circuit (metal resistance, bond wire resistance/inductance, etc.). You might check to see if the pins being damaged have the lowest package resistance or inductance. Resistance limits the peak current while inductance slows the rising edge.

Hope this gives you something more to look at.

Good Luck finding the cause.
 

DoctorProf,

Thanks for the input. How do you check whether the capacitance of the pin? And which capacitance you refer to, is it total capacitance of the discharge path or the testing system?

I am not expert in esd, but now I am part of the working group on this especially from wafer fab standpoint.

Is the junction capacitance for PN junction ( diode ) a big factor?
 

The capacitance of a node is a sum of the junction capacitance and inteconnect capacitance connected to that node. CDM typically is done in a "DEADBUG" configuration and the part is placed on an inuslating materail in the test fixture. A plate under the fixture is charged inducing a charge on the part or device under test (DUT). If you have a sensitive capacitance meter you can measure the pin capacitance by placing the part on a conductive plate. Connect the capacitance meter between the plate and a pin.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top