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  1. #1
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    Multi-source in Unit <dpram> on signal <Mcount_addr_12>; this signal is connected to

    Hi,
    I am using dual port ram as two single port ram of diiferent width, one with 11 & other with 9. this is required for designing nand flash memory controller.one port is used for sending 2048 bytes to nand flash and the other port for sending 512 bytes to ecc module to generate parity bits.
    i am getting these errors for dual port ram alone(not yet integrated with any other module).

    Here is the code
    module dpram(
    clk,clk1, // Clock Input
    address_0 , // address_0 Input
    data_0,
    cs_0 , // Chip Select
    we_0 , // Write Enable/Read Enable
    re_0 , // Output Enable
    address_1 , // address_1 Input
    data_1 , // data_1 bi-directional
    cs_1 , // Chip Select
    we_1 , // Write Enable/Read Enable
    re_1 , // Output Enable
    data_out0,
    data_out1
    );

    //--------------Global Parameters-----------------
    parameter DATA_WIDTH = 8 ;
    parameter ADDR_WIDTH0 = 8 ;
    parameter ADDR_WIDTH1 =8;
    parameter RAM_DEPTH0 = 1 << ADDR_WIDTH0;
    parameter RAM_DEPTH1 = 1 << ADDR_WIDTH1;

    //--------------Input Ports-----------------------
    inout [ADDR_WIDTH0-1:0] address_0;
    inout [ADDR_WIDTH1-1:0] address_1;
    input cs_0,clk,we_0,re_0 ;
    input cs_1,clk1,we_1,re_1;
    inout [DATA_WIDTH-1:0] data_0,data_1;

    //--------------Internal variables----------------
    reg [DATA_WIDTH-1:0] mem0 [0:RAM_DEPTH0-1];
    reg [DATA_WIDTH-1:0] mem1 [0:RAM_DEPTH1-1];
    reg [ADDR_WIDTH0-1:0] addr_0;
    reg [ADDR_WIDTH1-1:0] addr_1;
    reg [DATA_WIDTH-1:0] data0,data1;

    //--------------Output Ports----------------
    output reg [DATA_WIDTH-1:0] data_out0 ;
    output reg [DATA_WIDTH-1:0] data_out1 ;

    //--------------Code Starts Here------------------

    initial
    begin
    addr_0=0;
    addr_1=0;
    data0=0;
    data1=0;
    end


    assign address_0=addr_0;
    assign address_1=addr_1;
    assign data_0=data0;
    assign data_1=data1;


    // Memory Write Block
    // Write Operation : When we_0 = 1, cs_0 = 1
    always @ (posedge clk)
    begin : MEM_WRITE
    if ( cs_0 && we_0 )
    begin

    mem0[address_0] <= data_0;
    end
    end

    always @ (posedge clk1)
    begin : MEM_WRITE1
    if (cs_1 && we_1)
    begin
    mem1[address_1] <= data_1;
    end
    end



    always@(posedge clk)
    begin
    if ( cs_0 && we_0 )
    begin
    addr_0=addr_0+1;
    data0=data0+1;
    end
    end


    always@(posedge clk1)
    begin
    if ( cs_1 && we_1 )
    begin
    addr_1=addr_1+1;
    data1=data1+1;
    end
    end



    // Memory Read Block
    // Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1
    always @ (posedge clk)
    begin : MEM_READ_0
    if (cs_0 && ! we_0 && re_0)
    begin

    data_out0 <= mem0[address_0];

    end
    else
    begin
    data_out0 <= 0;
    end
    end

    always@(posedge clk)
    begin

    if (cs_0 && ! we_0 && re_0)
    addr_0=addr_0+1;

    end

    //Second Port of RAM
    // Memory Read Block 1
    // Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 1
    always @ (posedge clk1)
    begin : MEM_READ_1
    if (cs_1 && ! we_1 && re_1) begin
    data_out1 <= mem1[address_1];
    end else begin
    data_out1 <= 0;
    end
    end


    always@(posedge clk1)
    begin
    if (cs_1 && ! we_1 && re_1)
    addr_1=addr_1+1;
    end
    endmodule

    Errors are as follows
    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_0_cy<0>>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_0_0>
    Output signal of FDE instance <addr_0_ren_0>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_02>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_0_1>
    Output signal of FDE instance <addr_0_ren_1>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_04>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_0_2>
    Output signal of FDE instance <addr_0_ren_2>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_06>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_0_3>
    Output signal of FDE instance <addr_0_ren_3>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_08>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_0_4>
    Output signal of FDE instance <addr_0_ren_4>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_010>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_0_5>
    Output signal of FDE instance <addr_0_ren_5>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_012>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_0_6>
    Output signal of FDE instance <addr_0_ren_6>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_014>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_0_7>
    Output signal of FDE instance <addr_0_ren_7>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_1_cy<0>>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_1_0>
    Output signal of FDE instance <addr_1_ren_0>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_12>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_1_1>
    Output signal of FDE instance <addr_1_ren_1>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_14>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_1_2>
    Output signal of FDE instance <addr_1_ren_2>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_16>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_1_3>
    Output signal of FDE instance <addr_1_ren_3>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_18>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_1_4>
    Output signal of FDE instance <addr_1_ren_4>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_110>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_1_5>
    Output signal of FDE instance <addr_1_ren_5>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_112>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_1_6>
    Output signal of FDE instance <addr_1_ren_6>

    ERROR:Xst:528 - Multi-source in Unit <dpram> on signal <Mcount_addr_114>; this signal is connected to multiple drivers.
    Drivers are:
    Output signal of FDE instance <addr_1_7>
    Output signal of FDE instance <addr_1_ren_7>


    Total REAL time to Xst completion: 4.00 secs
    Total CPU time to Xst completion: 3.63 secs

    -->

    Total memory usage is 203392 kilobytes

    Number of errors : 16 ( 0 filtered)
    Number of warnings : 0 ( 0 filtered)
    Number of infos : 4 ( 0 filtered)

    Kindly please do solve this problem

    thank you

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  2. #2
    Full Member level 4
    Points: 2,726, Level: 12

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    Re: Multi-source in Unit <dpram> on signal <Mcount_addr_12>; this signal is connected

    without saying what I think of the rtl itself...
    one error is here:

    Code:
    always@(posedge clk)
      if ( cs_0 && we_0 ) 
        begin
        addr_0=addr_0+1;
        //....//
    always@(posedge clk)
      if (cs_0 && ! we_0 && re_0) 
        addr_0=addr_0+1;
    the second is similar;

    shortly: you can't assign values to the same node
    in multiply 'always' block, this gives
    'multisource error'

    a quick fix could be:
    Code:
      always@(posedge clk)
      if (( cs_0 && we_0 ) || (cs_0 && ! we_0 && re_0))
        addr_0=addr_0 + 1'b1;
    but you can do it in more elegant way;

    j.a
    Last edited by j_andr; 24th September 2012 at 14:40.



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