[SOLVED] 2D ARRAY problem (VHDL)

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity arrr is
    Port (  clk : in std_logic;
            data : out  STD_LOGIC_VECTOR (15 downto 0));
end arrr;
 
architecture Behavioral of arrr is
 
type m1 is array (0 to 1) of std_logic_vector(15 downto 0);
signal mem : m1;
 
begin
 
process(clk)
variable q : integer:=0;
variable r : std_logic_vector(15 downto 0);
begin
    if (rising_edge(clk))
        then
        if(q=0)
            then
            mem<=(others => (others => '0'));
            mem(0)<="1111111111001111";
            mem(1)(15 downto 0)<=mem(0)(15 downto 0);   -- THIS LINE IS NOT WORKING
            q:=1;
                        r:=mem(0)(15 downto 0);                     -- THIS IS ALSO NOT WORKING
 
         else
            data<=mem(1);
        end if;
    end if;
end process;
        
        
        
        
end Behavioral;

Code VHDL - [expand]
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data<=mem(0);