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puzzle on current MPEG decoder project

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hello everybody, currently many asic design houses work on MPEG decoder.
they seem to adop the similar architecture : MCU + DSP + some analog blocks,
I wonder what 's the most difficult in those kinds of design, hardware design or software programming or system debug?
Could someone explain working flow in this architecture?
Thanks alot
 

Hi,
Well the most tricky part of MPEG codec are the following
Software challenges:
1) IPC as the MPEG data is huge and need to be handled eficiently.
2) Memory management and buffer allotment.
3) Having wrappers at each level for the hardware.

Hardware challenges:
1) Providing endoced and decoded data with proper synchronization.
2) Adopting proper filtering so as to maximize the signal strength.

As for the hardware its always one-time development and then reuse. But ofcourse the software complexity of these systems are so huge that they need a bit of more detail. So the challenges are rather equipotent.
 

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