+ Post New Thread
Results 1 to 5 of 5
  1. #1
    Advanced Member level 1
    Points: 2,557, Level: 11

    Join Date
    May 2012
    Posts
    404
    Helped
    2 / 2
    Points
    2,557
    Level
    11

    The difference between "initial" and "always"

    Hi i want to know following verilog that

    1. The difference between initial and always.
    2. The difference between blocking assinment and nonblocking assignment.
    3. The difference between ifdef and generate.
    4. The difference between forever, repeat, while, for, do-while.
    5. The difference between flip-flop and latch.

    •   AltAdvertisement

        
       

  2. #2
    Banned
    Points: 866, Level: 6

    Join Date
    Feb 2012
    Location
    shenzhen, CN
    Posts
    96
    Helped
    9 / 9
    Points
    866
    Level
    6
    Blog Entries
    7

    Re: The difference between "initial" and "always"

    [QUOTE=u24c02;1140251]Hi i want to know following verilog that
    2. The difference between blocking assinment and nonblocking assignment.

    The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are distinguished by the = and <= assignment operators. The blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. For example, the following Verilog program

    // testing blocking and non-blocking assignment

    module blocking;
    reg [0:7] A, B;
    initial begin: init1
    A = 3;
    #1 A = A + 1; // blocking procedural assignment
    B = A + 1;

    $display("Blocking: A= %b B= %b", A, B ); A = 3;
    #1 A <= A + 1; // non-blocking procedural assignment
    B <= A + 1;
    #1 $display("Non-blocking: A= %b B= %b", A, B );
    end
    endmodule

    produces the following output:
    Blocking: A= 00000100 B= 00000101
    Non-blocking: A= 00000100 B= 00000100

    The effect is for all the non-blocking assignments to use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the current time unit. This reflects how register transfers occur in some hardware systems.
    blocking procedural assignment is used for combinational logic and non-blocking procedural assignment for sequential



    •   AltAdvertisement

        
       

  3. #3
    Full Member level 3
    Points: 1,713, Level: 9

    Join Date
    Nov 2009
    Location
    India
    Posts
    160
    Helped
    21 / 21
    Points
    1,713
    Level
    9

    Re: The difference between "initial" and "always"

    Better to go through any Verilog HDL book like sameer palnitkar.



    •   AltAdvertisement

        
       

  4. #4
    Banned
    Points: 1,915, Level: 10

    Join Date
    Feb 2011
    Location
    Bangalore
    Posts
    349
    Helped
    76 / 76
    Points
    1,915
    Level
    10

    Re: The difference between "initial" and "always"

    Initial Block will get executed only once start of the simulation.
    Always Block will get executed when ever it meets the condition to enter always block.



  5. #5
    Banned
    Points: 866, Level: 6

    Join Date
    Feb 2012
    Location
    shenzhen, CN
    Posts
    96
    Helped
    9 / 9
    Points
    866
    Level
    6
    Blog Entries
    7

    Re: The difference between "initial" and "always"

    Both latches and flip-flops are circuit elements whose output depends not only on the current inputs, but also on previous inputs and outputs.

    The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always does.Latches are asynchronous, which means that the output changes very soon after the input changes.A flip-flop is a synchronous version of the latch.
    Latch is a level sensitive device and flip-flop is edge sensitive device. Latch is sensitive to glitches on enable pin, where as flip-flop is immune to gltiches.
    Latches take less gates (also less power) to implement then flip-flops.
    Latches are faster then flip-flops.

    this is how the output of the two will differ:

    the output of the latch will be the same as the data input as it does not have a clock signal whereas in a flipflop there would be a delay of one clock cycle to see the output.
    pooja

    Read more: Difference between flip-flops & latches | Answerbag http://www.answerbag.com/q_view/436819#ixzz26nVlLYyn



--[[ ]]--