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Mixed signal simulation with rtl (co sim)

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olaf01555

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Hi All,
I am having a analog circuit in my schematic editor and I instantiated a symbol (created it using VerilogIn from rtl code).
Now when I was trying to run Cadence ams simulation I was getting an error.
I can able to run ams simulations successfully with veriloga, But I am not sure why I was not able to run using rtl code.
Any inputs...
 

first,you must build a new view named "config“。
you can find a guide lab in $CDSHOME/tools/dfII/samples/AMS.
tyr it.
 
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