Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

why there should be n well spacing

Status
Not open for further replies.

vivekrajeev

Junior Member level 2
Joined
Feb 24, 2011
Messages
24
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Location
bangalore
Activity points
1,434
Hi
Why is that nwell spacing is required. What happens if I dont give ? Dont tell me that it is in the rule book and thats why we are giving :p
 

wells at different potential needs to be apart orelse it will be in same potential shorting wells
 

where should there be N spacing

CMOS and most devices have spacing to prevent the internal shorting
 

There's a manufacturability gap where you can't reliably
pattern below a certain spacing. Zero gets merged, any
as-printed spacing less than your well depth has a chance
of the implant drive connecting them anyway.

Then there's the question of just what a narrow-base
lateral NPN looks like, to your circuit.
 

Then there's the question of just what a narrow-base
lateral NPN looks like, to your circuit.

So you say that it forms an extra npn transistor which is unintended right? Thats the reason we give spacign and one more is the manufacturability thing.
Thanks for the answer dick
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top