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How to design a CML Negative edged D Latch

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anushkannan81

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I have designed a CML D latch. but to proceed for frequency divider, i have to connect clock input to Positve edge of One latch and negative edge of another latch. So two latches are connected and ouput of negative edge is fed back as input to first D latch. Kindly reply me how to proceed.
 

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