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How can we meet timing ("SLACK MET") and none zero "DESIGN RULE COST" together?

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alexhugo

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How can we meet timing ("SLACK MET") and have none zero "DESIGN RULE COST" together?

Hi,
I am synthesizing a circuit (using DC) and I see that the timing is met (SLACK MET) by using report_timing. The problem is that "DESIGN RULE COST" is not zero. As far as I know none zero design rule cost means that the timing is not met.
What am I making wrong? How is possible to have these two together?
Thanks
Alex
 
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Re: How can we meet timing ("SLACK MET") and none zero "DESIGN RULE COST" together?

Hi Alex,

DRC is the violation in your max_cap or max_tran values and nothing to do with slack. DRC is given more importance than timing. U have to rectify the DRC error and only then u have to c the slack.
 

Re: How can we meet timing ("SLACK MET") and none zero "DESIGN RULE COST" together?

I know how DRC works in analog design but I don't know where to start working on it and fixing it in digital circuit.
Could you please help me and let me know where I should start and what I should do to fix the DRC issue in my digital ASIC design!?
 

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