phuang
Junior Member level 1
Values of pull up PMOS, pull down NMOS driver & access NMOS transistor for 32nm SRAM
Hello everyone, I need your help! Thank you in advance.
Does anyone know the approximate value for the pull up PMOS, the Pull down NMOS driver, and access NMOS transistor for 40nm or 32nm sram cell? I just need a approximate value for reference.
We want to do a hspice simulation for a sram cell using PTM 32nm library. But we don't know how to determine the proper size for the MOS transistros, not the cell ratio, and pull up ratio, it is the value of the width of the six transistors. we need a baseline. We My teammates thought we can use any value when using the PTM 32nm model, while I found some warning in the HSPICE output list files, like " + width, too small ","the acde =1, too small"
I referred some paper, some used 80/40(PMOS),120/40 (NMOS), 120/40 (NMOS) for 32nm, some used 400/45nm PMOS, 200/45nm NMOS for 45nm process.
P.S., we know the way to determine the cell ratio and the pull up ratio.
Thanks again!
Hello everyone, I need your help! Thank you in advance.
Does anyone know the approximate value for the pull up PMOS, the Pull down NMOS driver, and access NMOS transistor for 40nm or 32nm sram cell? I just need a approximate value for reference.
We want to do a hspice simulation for a sram cell using PTM 32nm library. But we don't know how to determine the proper size for the MOS transistros, not the cell ratio, and pull up ratio, it is the value of the width of the six transistors. we need a baseline. We My teammates thought we can use any value when using the PTM 32nm model, while I found some warning in the HSPICE output list files, like " + width, too small ","the acde =1, too small"
I referred some paper, some used 80/40(PMOS),120/40 (NMOS), 120/40 (NMOS) for 32nm, some used 400/45nm PMOS, 200/45nm NMOS for 45nm process.
P.S., we know the way to determine the cell ratio and the pull up ratio.
Thanks again!
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