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ncverilog: ncelab error cuvmur

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sonofflynn

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I am currently having an issue with ncelab when using ncverilog in Virtuso. I keep getting error messages like the following:

nfetx M1 ( .S(cds_globals.gnd_), .G(net11), .D(Y),
|
ncelab: *E,CUVMUR (./ihnl/cds0/netlist,18|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M1' of design unit 'nfetx' is unresolved in 'worklib.AND2X1:verilog'.
nfetx M2 ( .S(cds_globals.gnd_), .G(B), .D(hnet14),
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ncelab: *E,CUVMUR (./ihnl/cds0/netlist,20|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M2' of design unit 'nfetx' is unresolved

Here is what I did:
I synthesized a design with Design Compiler and then imported the verilog netlist into Virtuoso to create a schematic. Next, I opened NC-Verilog in Virtuoso and selected the schematic as the top level design. I initialized and generated the netlist for the design. However, I run into problems when I try to simulate.
 

i think you need to import the library as well that has basic gates like AND2X1, etc
 

Do you mean the the library with my standard cells? If so, I have a '.v' file associated with all the standard cells and also the normal library with schematic, symbol, and layout information for all the standard cells. Which one are you referring to? And also, how would I import it? Thanks.

It seems like all of the errors are related to nfet and pfet instances within the standard cell gates used my design.
 
Last edited:

sonofflynn said:
I am currently having an issue with ncelab when using ncverilog in Virtuso. I keep getting error messages like the following:

nfetx M1 ( .S(cds_globals.gnd_), .G(net11), .D(Y),
|
ncelab: *E,CUVMUR (./ihnl/cds0/netlist,18|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M1' of design unit 'nfetx' is unresolved in 'worklib.AND2X1:verilog'.
nfetx M2 ( .S(cds_globals.gnd_), .G(B), .D(hnet14),
|
ncelab: *E,CUVMUR (./ihnl/cds0/netlist,20|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M2' of design unit 'nfetx' is unresolved

Here is what I did:
I synthesized a design with Design Compiler and then imported the verilog netlist into Virtuoso to create a schematic. Next, I opened NC-Verilog in Virtuoso and selected the schematic as the top level design. I initialized and generated the netlist for the design. However, I run into problems when I try to simulate.
Click to expand...


ncverilog requires files ordering for correct compilation. Otherwise you will got error.
Example.
assume we the following files
a.v
b.v
and b module is instantiated in a.v file.
so you should call ncverilog like this:

ncverilog b.v
ncverilog a.v

otherwise you will got above mentioned ERROR
I don't know what is the flag for ncverilog command to avoid ordering of verilog files ((

- - - Updated - - -

Does ncverilog have that flag ?
 

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