Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why is write and read levelling technique is completely different in DDR3?

Status
Not open for further replies.

vipul982

Junior Member level 3
Joined
Feb 2, 2010
Messages
30
Helped
0
Reputation
0
Reaction score
2
Trophy points
1,288
Location
India
Activity points
1,465
Hi guys,

I wnated to know why write and read levelling technique is completely different in DDR3? are both of them done to synchronize between clock and DQS signal? I am not clear as to why both technique is different even though same result is targeted...
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top