XST Synthesis - Synthesis Report

Dear all.



I am running a synthesis for some componennts of the router I have build in VHDL. My goal is to have latency and throughput resuts for the router.



The thing is thath I am trying to understand the difference between the default period analysis (green) and the following red analysis! What is the difference between them? They represent different delay for paths inside the component? Which one is the dominant and I need to worry about?



In addition to see if I am getting things right! 1) The lower the Level Of Logic the better. 2) The Speed Grade is -3 for this synthesis, where for the VIRTEX-5-6 FGPAs is the on with the better performance right and it defines the timing performance of the device?



Thank you in advance.



Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.033ns (frequency: 491.836MHz)
Total number of paths / destination ports: 210 / 20
-------------------------------------------------------------------------
Delay: 2.033ns (Levels of Logic = 3)
Source: pre_req_2 (FF)
Destination: pre_req_2 (FF)
Source Clock: clk rising
Destination Clock: clk rising

Data Path: pre_req_2 to pre_req_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 5 0.361 0.530 pre_req_2 (pre_req_2)
LUT5:I2->O 8 0.097 0.543 mask_pre<2>1 (mask_pre<2>)
LUT5:I2->O 2 0.097 0.299 GND_4_o_mask_pre[4]_not_equal_11_o (GND_4_o_mask_pre[4]_not_equal_11_o)
LUT6:I5->O 1 0.097 0.000 Mmux_win32 (win<2>)
FDRE 0.008 pre_req_2
----------------------------------------
Total 2.033ns (0.660ns logic, 1.373ns route)
(32.5% logic, 67.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 211 / 30
-------------------------------------------------------------------------
Offset: 1.950ns (Levels of Logic = 4)
Source: full_local (PAD)
Destination: pre_req_4 (FF)
Destination Clock: clk rising

Data Path: full_local to pre_req_4
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
LUT4:I0->O 8 0.097 0.715 Madd_req[4]_GND_4_o_add_9_OUT_cy<2>11 (Madd_req[4]_GND_4_o_add_9_OUT_cy<2>)
LUT5:I0->O 1 0.097 0.000 Mmux_win5_SW0_SW0_G (N54)
MUXF7:I1->O 1 0.279 0.379 Mmux_win5_SW0_SW0 (N41)
LUT6:I4->O 1 0.097 0.000 Mmux_win5 (win<4>)
FDRE 0.008 pre_req_4
----------------------------------------
Total 1.950ns (0.855ns logic, 1.095ns route)
(43.9% logic, 56.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Offset: 0.361ns (Levels of Logic = 0)
Source: grant_q_4 (FF)
Destination: grant<4> (PAD)
Source Clock: clk rising

Data Path: grant_q_4 to grant<4>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 1 0.361 0.000 grant_q_4 (grant_q_4)
----------------------------------------
Total 0.361ns (0.361ns logic, 0.000ns route)
(100.0% logic, 0.0% route)

=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay: 0.113ns (Levels of Logic = 1)
Source: full_local (PAD)
Destination: wr_en_local (PAD)

Data Path: full_local to wr_en_local
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
INV:I->O 0 0.113 0.000 wr_en_local1_INV_0 (wr_en_local)
----------------------------------------
Total 0.113ns (0.113ns logic, 0.000ns route)
(100.0% logic, 0.0% route)

=========================================================================

firstly, most designs will specify the timing requirements and not use the "automatically constrain" option. Look at Xilinx's "constraints guide" for more info.

Period -- between synchronous elements that are clocked by the same, or known-related clocks.
Input -- used to show that data arriving at a data pin on the FPGA will meet setup/hold when clocked by a clock derived from the input clock pin.
Output -- not useful anymore. Shows the delay in generating an output from a clock derived from a clock pin. High speed interfaces will be source-synchronous (will provide a clock that is aligned to the output data), which removes the need for these constraints.
Path -- between elements in the FPGA. Possibly used to tell the tools that some paths do not need to be constrained despite a period constraint being applicable. (eg, some clocks might be synthesized from the same source, but are intended to be treated as asynchronous in the FPGA. the period constraint might find impossible requirements, like 10 ps) Likewise to provide constraints where none otherwise exist. (eg, gray-coded counters are only valid when there is less than one rx cycle of skew on the bus. the path constraints can be used for this). Finally, they can be used for multicycle constraints to inform the tools that the data doesn't change every cycle, and that the data is used in a way to allow for extra setup time.

Thank you for your reply Permute!!!

So if I am getting it right the period one is the one I am interested in!The delay mentioned in this section is the delay that this component will introduce to the top level module?

Could you please clarify for me the Level Of Logic and the Speed of Grade?
The lower the Level Of Logic the better. 2) The Speed Grade is -3 for this synthesis, where for the VIRTEX-5-6 FGPAs is the on with the better performance right and it defines the timing performance of the device!

Any other data in the synthesis that I must take into account in order to see the latency of the component?

As for the constrains I am on it!!!

Thank you again, much appreciated.