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Problem in adding Revised design in LEC Conformal

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amitk3553

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I m having following types of errors when adding revised design in Conformal .Read Design failed. :---

Error: /projects/MC_E_E1/wrk/amkumar/trunk/trunk/results/synasic/spi/0824.0929/op_data/spi.1st.v:73 Module 'or21d1' is referenced but not defined.

What does it mean????
Please Reply
Thanks
 

pls check - this is an empty module or not defined correctly

Do you see any defiitions for or21d1?
 

englishdogg said:
pls check - this is an empty module or not defined correctly

Do you see any defiitions for or21d1?
Click to expand...

frnd I have checked its netlist in verilog.
where I found following heirarchy:
e.g.
module wb_ram ( clk_i, adr_i, dat_i, cyc_i, we_i, stb_i, mem_dat_o, rdout,
dat_o, ack_o, addr, clk_o, csn, wr, d );
input [15:0] adr_i;
input [7:0] dat_i;
input [7:0] mem_dat_o;
output [7:0] dat_o;
output [8:0] addr;
output [7:0] d;
input clk_i, cyc_i, we_i, stb_i, rdout;
output ack_o, clk_o, csn, wr;
wire n29, n30;

ni01d2 U7 ( .i(dat_i[0]), .z(d[0]) );
ni01d2 U8 ( .i(dat_i[1]), .z(d[1]) );
ni01d2 U9 ( .i(dat_i[2]), .z(d[2]) );
ni01d2 U10 ( .i(dat_i[3]), .z(d[3]) );
ni01d2 U11 ( .i(dat_i[4]), .z(d[4]) );
ni01d2 U12 ( .i(dat_i[5]), .z(d[5]) );
ni01d2 U13 ( .i(dat_i[6]), .z(d[6]) );
ni01d2 U14 ( .i(dat_i[7]), .z(d[7]) );
ni01d2 U15 ( .i(we_i), .z(wr) );
ni01d2 U16 ( .i(adr_i[0]), .z(addr[0]) );
ni01d2 U17 ( .i(adr_i[1]), .z(addr[1]) );
ni01d2 U18 ( .i(adr_i[2]), .z(addr[2]) );
ni01d2 U19 ( .i(adr_i[3]), .z(addr[3]) );
ni01d2 U20 ( .i(adr_i[4]), .z(addr[4]) );
ni01d2 U21 ( .i(adr_i[5]), .z(addr[5]) );
ni01d2 U22 ( .i(adr_i[6]), .z(addr[6]) );
ni01d2 U23 ( .i(adr_i[7]), .z(addr[7]) );
ni01d2 U24 ( .i(adr_i[8]), .z(addr[8]) );
ni01d2 U25 ( .i(mem_dat_o[0]), .z(dat_o[0]) );
ni01d2 U26 ( .i(mem_dat_o[1]), .z(dat_o[1]) );
ni01d2 U27 ( .i(mem_dat_o[2]), .z(dat_o[2]) );
ni01d2 U28 ( .i(mem_dat_o[3]), .z(dat_o[3]) );
ni01d2 U29 ( .i(mem_dat_o[4]), .z(dat_o[4]) );
ni01d2 U30 ( .i(mem_dat_o[5]), .z(dat_o[5]) );
ni01d2 U31 ( .i(mem_dat_o[6]), .z(dat_o[6]) );
ni01d2 U32 ( .i(mem_dat_o[7]), .z(dat_o[7]) );
nr21d1 U33 ( .a1(n29), .a2(csn), .zn(clk_o) );
in01d1 U34 ( .i(clk_i), .zn(n29) );
nr21d1 U35 ( .a1(csn), .a2(n30), .zn(ack_o) );
nr21d1 U36 ( .a1(rdout), .a2(we_i), .zn(n30) );
nd21d1 U37 ( .a1(stb_i), .a2(cyc_i), .zn(csn) );
endmodule


I found modules like above in netlist file.And I am finding this problem at all gates like nd 21d1.NOW tell me where i have to check whether its empty module or defined correctly or not.
Thanks
 
Last edited:

amit

Pls see the lec log - in the snippet you ahve posted above i do not see any reference to "or21d1"
 

englishdogg said:
amit

Pls see the lec log - in the snippet you ahve posted above i do not see any reference to "or21d1"
Click to expand...

or21d1 was for other IP.
Here I had taken the example of small IP.
All the gates shown in RED are having the same problem....It is said for all gates in red that they are referenced but not defined.So plese explain it that where I have to define these and how.


Thanks for response.
 

from your last append I am almost sure you are not reading the libraries (technology libs) using which the netlist was synthesized - if you are then any one lib is missing
 
englishdogg said:
from your last append I am almost sure you are not reading the libraries (technology libs) using which the netlist was synthesized - if you are then any one lib is missing
Click to expand...

Yup its solved...Technology library was missing.
Thanks for your help
 

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