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NMOS drain does not connect with VDD, PMOS drain does not connect with GND,why?

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threekingtiger

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Today I was told by a guy that I would better not connect the drain of NMOS with VDD directly in NMOS source follower and not
connect the drain of PMOS with GND in PMOS source follower. That's obviously not mentioned in text books.

Could someone tell me why? For ESD consideration?For Latch-up consideration? I've no idea.
 

I work in an 8V SiGe BiCMOS process. We have VCC GND=0 and VEE! Probably you are a digital designer! :p
 

threekingtiger said:
... better not connect the drain of NMOS with VDD directly in NMOS source follower
and not connect the drain of PMOS with GND in PMOS source follower.
Click to expand...

IMHO there's no reason to avoid such a connection, after all it's the standard connection for source followers.

For complementary source followers, however, the layout guy should be informed not to get the two drains (of such a complementary source follower pair) too close, because then the created lateral (p+ n p n+) thyristor structure is prone to latchUp, which in this case would be lethal.

Here, an indirect connection to GND resp. VDD (e.g. via current limiting inverters) would prevent such a latchUp disaster.
 

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