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  1. #1
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    Difference between Source Synchronous and Synchronous System

    Difference between Source Synchronous and Synchronous System

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    Re: Difference between Source Synchronous and Synchronous System

    You may be confusing some terms.

    "Source" synchronous and a "System" synchronous are Input/Output (IO) concerns. In source synchronous, the source provides a clock and the data that is valid with the provided clock. RGMII and DDR2/3 and many high-speed parallel ADC/DACs are examples.

    System Synchronous is more of a legacy, lower speed method. In this case a third party (external osciallator is common) provides the clock to both the transmitting and recieving party. eg, an oscillator provides a 33MHZ clock to your ASIC as well as an external RAM.

    System synchronous has issues for higher speeds. For example, lets say an external oscillator gives a 1000MHz clock to both your ASIC and an external DAC. You must receive the 1000MHz clock and output data from your ASIC with an appropriate delay for the clock received at the external DAC. Now even small differences in the clock routing become important.


    A synchronous design itself is just one were operation occur on clock edges only, and not on other signal changes/levels.



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    Re: Difference between Source Synchronous and Synchronous System

    Let me put question differently.
    Difference between Source Synchronous system and Synchronous System



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  4. #4
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    Re: Difference between Source Synchronous and Synchronous System

    An example of this may the hierarchical levels of stability for Stratum I,II & III clocks used for synchronous networks. The clock is derived from the data source with defined Stratum level and regenerated with best source available from multiple choices of sources. An insular network is isolated and requires no outside reference. A plesiochronous network is pseudo synchronous to an outside reference, which have source defined stability reference (Stratum Level).. This allow for frequency error such as 1e-11, 1e-9, 1e-7 etc and local jitter is reduced by tracking data edges. This optimized data recovery while maintaining flow for synch'd network paths to avoid frame slip or buffer. The requirements are designed to minimize latency in a network, yet maximize channel utilization.

    The specs for this can fill a room with books.

    For more detail look up PDH and SDH.
    A good design question lists your overall requirements™ The best question deserves a better answer. ™
    ... Tony Stewart EE since 1975



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