Relation between input and output delay of a circuit and circuit max frequency ?

Can someone please describe the effect of input delay and output delay on the maximum operating frequency of a circuit ?
I knew that max operating frequency of a given digital circuit depends on Tclktoq of launching flop + net delay + combo delay + setup time of receiving flop +/- clock skew. But I could not understand whether input delay and output delay of a given circuit would have any impact on maximum operating frequency.




In this diagram, what is the maximum operation frequqnecy of the circuit under following cicumstances ?

1. in is launched by clk and out is captured by clk.
2. in is launched by an async clock and out is captured by clk.
3. in is launched by clk and out is captured by an async clock.
4. in is launched by an async clock and out is captured by an async clock.
5. in is launched by clk/2 and out is captured by clk/4.


Thanks
Vasanth

Input output Delay matters when other chip also works on same frequency as yours and it is also seen as reg to reg path

Thanks subash and dftrtl. My opinion also coincides with your thoughts.
But I would like to get an answer from more seasoned edaboarders and also would like to understand how STA tool treats input delay and output delay definitions during maximum frequqnecy calculation.