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Data Sharing among various process....Please Help

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nikhilsigma

nikhilsigma

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I have to design a simple server model....

in my design it is required to update a status(which is an integer value), now this value also needs to be shared and updated in various processes.
so i can't have a variable for this.....as it is defined in one process only...
also i can't have a signal for this value....as it can be assigned only in one process.....

so i am not able to make this value global and also update it everywhere... :(

please help.... :-?
 

You can have a process that will accept input from the various other processes that want to update your signal. Depending on how fancy you want (or need) to be, you can have handshaking between this master arbiter and the other processes to determine who gets to change the signal.
 

can u please help me with this....

Function: A storage server receives requests for accesses to data from one of 4 disks. The server
maintains a different request queue for every disk, and when it receives a request, it adds it to the
queue for the respective disk. Assume that each access keeps the disk busy for 2 seconds, and only
one of the disks can transfer data at a time. If requests to multiple disks are pending, it should use
some strategy to resolve the situation. All requests must be serviced.
Inputs: 4 switches, indicating whether access is requested to the respective disk. Switch is HIGH
means there is a request for a new access. To initiate a new access, turn the switch OFF and then
turn it ON after some time.
Outputs: 4 sets of 3 LED lights each, representing the status of 4 disks. GREEN means ready to accept
new request. RED means data transfer is in progress. ORANGE/YELLOW means requests are queued
for the disk.

i was thinking of making 4 processes for counting requests for 4 disks. and one common program which will check the counter and will wait for 2secs....
but i am having problem while updating counter..... :(
 

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity server is
    Port ( a : in  STD_LOGIC;   -- a is the rquests from the user
           b : in  STD_LOGIC;
           c,d: out  STD_LOGIC:='0');  -- c is showinh the processing of disk according to request(a)...
end server;
 
architecture Behavioral of server is
signal a1 :integer:=0;
signal a2 :std_logic := '0';
begin
 
    reqA : process (a,a2)   -- This process will count request in signal a1
    begin
        if(a' event and a='1')
            then a1<=a1+1;
            else a1<=a1;
        end if;
        if(a2='1')              -- signal a2 is used to indicated the processing and thus decrement of counter a1
            then a1<=a1-1;
--          else a1<=a1;
        end if;
    end process reqA;
    
    -- This process will be processing the requests( will wait for some time) 
    -- and then will update a2 which will then decrement a1 in above process...
    logic : process 
    begin
    wait for 1 ns;
        if(a1>0)
            then 
            c<='1';
            a2<='1';
            wait for 50 ns;  -- PROCESSING DELAY : problem comes when i try to increase this 
                            --delay(which is representing processing time) beyond half the time interval between two requests...
            else
            a2<='0';
            c<='0';
        end if;
    end process logic;
 
 
 
end Behavioral;









Problem is coming when the processing delay is increased.....please help........as program should give output at c for each input at a irrespective of the processing delay.....

here are the snaps of output....

1.jpg

2.jpg


PLEASE HELP

- - - Updated - - -

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity yo is
    Port ( a : in  STD_LOGIC;   -- a is the rquests from the user
           b : in  STD_LOGIC;
           c,d: out  STD_LOGIC:='0');  -- c is showinh the processing of disk according to request(a)...
end yo;
 
architecture Behavioral of yo is
signal a1 :integer:=0;
signal a2 :std_logic := '0';
begin
 
    reqA : process (a,a2)   
    begin
        if(a' event and a='1')
            then a1<=a1+1;
            else a1<=a1;
        end if;
        if(a2' event and a2='1')              
            then a1<=a1-1;
--          else a1<=a1;
        end if;
    end process reqA;
    
    
    logic : process 
    begin
    wait for 1 ns;
        if(a1>0)
            then 
            c<='1';
            a2<='1';
            wait for 150 ns;  
            elsif (a1=0)
            then
            a2<='0';
            c<='0';
        end if;
    end process logic;
 
 
 
end Behavioral;



i have improved the code....as the value of a1 was going negative....but still i am having problem when "Processing time is more then the time between two requests.....

please help.....
 
Last edited:

Don't use wait for your code; that's really just for test benches.

Also, you've got two statements inside one process that both assign values to a1. You need to totally rethink your approach here. Think hardware, not software.
 
so one signal can be updated only once in a process ??

what do you mean by think hardware.....can you suggest me some reading material, most of the text books tell about simulatable code...
 

In a synchronous process the signal only gets updated once. For example, the D-input of a flip-flop can change a hundred times before the clock edge occurs, but the Q output will only reflect the most recent input.

When i say 'think hardware' I mean think about the actual hardware that will be created from your VHDL.
 
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