Do you guys really use the function & Procedure in VHDL?

Re: Do you guys really use the function & Procedure in V

I believe function and procedure are useful in VHDL for both simulation and synthesis.

It is actually a kind of abstraction and hence leads to better code maintainance and design reuse. Although the function and procedure sound like sub-routine in the software, they are really different. You might tread a VHDL function like a normal piece of software function. But when you using the procedure, it's good to have a clear picture about what kind of hardware the procedure will be. Otherwise, your procedure may not be synthesisable. (please refer to IEEE 1076.6 for synthsisable sub-set of the VHDL.)

For example, you can use fuction to do type convert; you can use procedure for encoding/coding a composite signal. And they can be used for both simulation and synthesis.

Re: Do you guys really use the function & Procedure in V

i need help here then,,,

my question is when designing quite large and complicated system.......i will building the sub-module 1st then combine it to bcome a system.....i use to do it by schematic....hahhaa,,its beginner stuffs...

now i gonna try wth VHDL.....if without using function,,,,,how to build the submodule.....

since there is so many people can do tht wthout function,,,,,could u guys tell me how to do it wthout function.....

i think for few nites D on how to build the sys in hierachical way wthout using function.,,i duuno...any other way...

many many many thanxs,,,,

¾λ²

Re: Do you guys really use the function & Procedure in V

I believe everybody build his own experience and although the reuse-methodology is fine, but it is niether bible nor any holly book.
I do use function and procedures to do synthesized code and guess what it works just fine with me. I even used functions and procedures to pass my attributes some values and it worked, So functions save me time and effort, why wouldn't I use it. and till now no function had made any synthesis problem with me, and for the record I have more troubles with records than I have with functions until now although I have used records some times in my code and I thought it would make it reuseable but guess what LS didn't agree with my opnion. So I had bad experience with records, so maestor can u give me some guidelines on how to use records in a synthesized code.

suppose I'm using a function twice in my code, of a specific block. Will the function be synthesized twice or once ? .. or the synthesis tool will be smart enough to understand if the functions operations are co-existing or exclusive from the timing point of view ?

Re: Do you guys really use the function & Procedure in V

How do you imagine sharing of logic resources? If you have a function, that performs addition of two numbers, used twice in a design. Shall the VHDL compiler create multiplexers at in- and outputs of the adder, based on an analysis, that the two function instances won't be used simultanously? Very unlikely, to my opinion.

The construct would be contradicting to the operation principle of parallel logic.

Re: Do you guys really use the function & Procedure in V

FvM said:

How do you imagine sharing of logic resources? If you have a function, that performs addition of two numbers, used twice in a design. Shall the VHDL compiler create multiplexers at in- and outputs of the adder, based on an analysis, that the two function instances won't be used simultanously? Very unlikely, to my opinion.

The construct would be contradicting to the operation principle of parallel logic.

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Did you read the whole thread or just my last reply ?