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How to reduce power at system level and RTL level?

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rogger123

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Power optimisation

hi,
can someone give me some techniques to reduce power at a system level. and various techniques that can be used to reduce power at RTL level.
i would be happy if i got some reference material too.
 

Re: Power optimisation

Hi rogger123:

Do you have doc of power compiler/prime power? These are good

materials, I think them meet your need. You can reference them.

wang1
 

Re: Power optimisation

hi,
as o now i do ont have it but can make arrangments for it. would it cover the current industry trends?
 

Power optimisation

There are already a few posts on this topic,

1. LOW POWER ASIC
hxxp://&postdays=0&postorder=asc&highlight=low+power

2. E-Book links saved from moderated requests & uploads
hxxp://&postdays=0&postorder=asc&highlight=low+power+vlsi

3. Looking for low-power digital IC expert and methodolody
hxxp://&postdays=0&postorder=asc&highlight=low+power+vlsi

4. Papers for Low Power VLSI- Proceedings IEEE
hxxp://&postdays=0&postorder=asc&highlight=low+power+vlsi


x -> t
Good luck!
 

Power optimisation

gate clocking, multi VDD and multi Vt is the way to go for the current trend in physical. I am not sure about RTL level
 

Power optimisation

For RTL, coding style is important,especially for state machine design. Good coding style can avoid glitch which will consume much power
 

Re: Power optimisation

1) at system level, you can refine your spec. and architecture,

adopt low power algorithm.

2) at rtl level, you can use gated clock or lower operating frequency.




rogger123 said:
hi,
can someone give me some techniques to reduce power at a system level. and various techniques that can be used to reduce power at RTL level.
i would be happy if i got some reference material too.
Click to expand...
 

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