achundur
Junior Member level 1
Hi all :
I synthesized a VHDL design and the post-layout (without SDF annotation) simuation is working. But when I tried to do back-annotated simulation of the design using Nc-sim by reading SDF file (generated by Design compiler) , I observed that clock signal is sampling the glitch instead of capturing the data. This occured because clock skew and the reason for clock-skew is clock-gating logic in clock-path.
How should I proceed now? When does the prime-time comes into picture? What is next step after synthesizing a desin in ASIC flow?
Thanks
I synthesized a VHDL design and the post-layout (without SDF annotation) simuation is working. But when I tried to do back-annotated simulation of the design using Nc-sim by reading SDF file (generated by Design compiler) , I observed that clock signal is sampling the glitch instead of capturing the data. This occured because clock skew and the reason for clock-skew is clock-gating logic in clock-path.
How should I proceed now? When does the prime-time comes into picture? What is next step after synthesizing a desin in ASIC flow?
Thanks