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    ASIC design flow QUESTION

    Hi all :

    I synthesized a VHDL design and the post-layout (without SDF annotation) simuation is working. But when I tried to do back-annotated simulation of the design using Nc-sim by reading SDF file (generated by Design compiler) , I observed that clock signal is sampling the glitch instead of capturing the data. This occured because clock skew and the reason for clock-skew is clock-gating logic in clock-path.

    How should I proceed now? When does the prime-time comes into picture? What is next step after synthesizing a desin in ASIC flow?

    Thanks

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    Re: ASIC design flow QUESTION

    After synthesis DFT logic is inserted into the synthesized netlist and this netlist is given to physical design team. Physical design does floorplanning, place, clock tree synthesis and routing. Prime time is timing analysis tool used to check whether we meeting timing constraints or not .
    http://en.wikipedia.org/wiki/Physica..._(electronics)


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    Re: ASIC design flow QUESTION

    Simple design flow from rtl to foundry:


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    Re: ASIC design flow QUESTION

    Quote Originally Posted by hairo View Post
    Simple design flow from rtl to foundry:
    This flow doesn't include dft process, like mbist, scan chain, atpg & bsd.
    If dft process above is included, the flow will be a bit longer.



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    Re: ASIC design flow QUESTION

    About the Primetime usability --
    Please refer below link --

    STA using EDA tools

    STA using EDA tools part 2

    I hope it will help u.
    -Vlsi Expert


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    Re: ASIC design flow QUESTION

    Quote Originally Posted by zeese View Post
    This flow doesn't include dft process, like mbist, scan chain, atpg & bsd.
    If dft process above is included, the flow will be a bit longer.
    That's correct as I'm not familiar with DFT flow. Here is the DFT flow using Synopsys tools:

    1. HDL design considering Testing
    ==> you can check Synopsys RTL TESTDRC check with DFT compiler
    ==> Memory : Memory BIST logic insertion

    2. Synthesis considering Scan : DC Compiler
    ==> compile -scan ( pre_compiled with scan)
    ==> this command make F/F ==> scan F/F
    ==> check_test or check_dft : check DFT Violation Rule

    3. SCAN insertion & make chain : Synopsys DFT compiler
    ==> insert_scan or insert DFT
    ==> this command make scan chain
    of course , we have to cofigure scan chain

    4. BSD(JTAG) insertion with Synopsys BSD compiler
    ==> insert_bsd
    ==> you can insert JTAG before synthesis.
    ==> Make BSD vector with BSD compiler

    5. ATPG with Synopsys Tetramax

    ==> make ATPG vector with Tetramax
    ==> get fault exact coverage
    ==> if you want , you can fault_simulation.

    6. Simulaiton ( ATPG , MBIST , JTAG)

    ==> simulate all vector with your simulator ( ncsim or vcs or others)
    Source: https://www.edaboard.com/thread8823.html#post35637

    I think those flow must be done before P&R step.

    Thank you.


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