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Asynchronous Counter problem

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akash_joshi

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I have designed a 5bit asynchronous counter using T-flip flops. The T-flip-flops have a asynchronous reset and it is working fine.But when i am reseting the the counter then all the 5 outputs of the counter are not going to zero only the lsb is going to zero and other remain sometimes at logic 1 or logic 0. I am not able to reset the counter properly i.e. when im resseting the counter no aal the bits are going to zero.What should i do?

Pl help....................
 

take "ACTIVE LOW " RESET pin for all the flip flops used in the ckt ....

consider a 2 i/p NAND gate ... the i/p's of NAND GATE are Q0 , Q2 ...........

the o/p of this NAND gate is connected to claer terminal to all the flip flops ........

now it will workz out ..........
 

ANEESH RAVURI said:
take "ACTIVE LOW " RESET pin for all the flip flops used in the ckt ....

consider a 2 i/p NAND gate ... the i/p's of NAND GATE are Q0 , Q2 ...........

the o/p of this NAND gate is connected to claer terminal to all the flip flops ........

now it will workz out ..........
Click to expand...


The problem is that my master-slave J-k flip flop (which is used as a T flip flop) is not resetting properly so can u tell me a configuration where we can asynchronously reset a J-K flip flop
 

akash_joshi said:
... a configuration where we can asynchronously reset a J-K flip flop
Click to expand...

See this schematic of an asynchronously resettable JK Master-Slave-FF from an Artisan Lib:

 

Some explanation would be helpful:
- asynchronous counter means ripple counter?
- are you sure the reset pulse duration is long enough
- to understand the issue we would need to see the gate level circuit
 

erikl said:
See this schematic of an asynchronously resettable JK Master-Slave-FF from an Artisan Lib:

Click to expand...

Thanks a lot..............the link u gave have solved the problem for now
 

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