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  1. #1
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    Errors in generating netlist in Cadence Capture CIS -> Allegro, what to do?

    Hello to everyone,

    I am new to the Cadence OrCAD Capture CIS and Allegro suite. Now I need to create a pcb with those tools. When I activate the generation of the netlist I get the following errors/warnings:
    Code:
    ********************************************************************************
    *
    * Netlisting the design 
    *
    ********************************************************************************
    Design Name:
    Y:\USER\S-WOLFC\SA\BOARDS\FPGA_INTERFACE\Signal_Aufnehmer\signal_aufnehmer.dsn
    Netlist Directory:
    Y:\USER\S-WOLFC\SA\BOARDS\FPGA_INTERFACE\Signal_Aufnehmer\allegro
    Configuration File:
    C:\Cadence\PSD_15.1\tools\capture\allegro.cfg
    
    Spawning... "C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "Y:\USER\S-WOLFC\SA\BOARDS\FPGA_INTERFACE\Signal_Aufnehmer\signal_aufnehmer.dsn" -n "Y:\USER\S-WOLFC\SA\BOARDS\FPGA_INTERFACE\Signal_Aufnehmer\allegro" -c "C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
    #1 Warning [ALG0016] Part Name "C_SMD_1206_1206_CAP_REFLOW_10P_1206_1206_CAP_WAVE" is renamed to "C_SMD_1206_1206_CAP_REFLOW_10P_".
    #2 Warning [ALG0016] Part Name "ELCAP_10UF_50V_CAP_ELCAP_50_110_RM20_10UF" is renamed to "ELCAP_10UF_50V_CAP_ELCAP_50_110".
    #3 Warning [ALG0016] Part Name "C_SMD_1206_1206_CAP_REFLOW_C_SMD_1206_1206_CAP_WAVE" is renamed to "C_SMD_1206_1206_CAP_REFLOW_C_SM".
    #4 Warning [ALG0016] Part Name "RJ45_8P_PCB_A_FEM_CONN_RJ45_8P_PCB_A_FEM_RJ45-8" is renamed to "RJ45_8P_PCB_A_FEM_CONN_RJ45_8P_".
    #5 Warning [ALG0016] Part Name "PCB_1X02_CONN_PCB_1_2_S_GMR_6_CONN_PCB_1_2_A_M, CONN_PCB_1_2_A_F" is renamed to "PCB_1X02_CONN_PCB_1_2_S_GMR_6_C".
    #6 Warning [ALG0016] Part Name "PCB_1X02_CONN_PCB_1_2_S_GMR_7_CONN_PCB_1_2_A_M, CONN_PCB_1_2_A_F" is renamed to "PCB_1X02_CONN_PCB_1_2_S_GMR_7_C".
    #7 Warning [ALG0016] Part Name "PCB_1X02_CONN_PCB_1_2_S_GMR_8_CONN_PCB_1_2_A_M, CONN_PCB_1_2_A_F" is renamed to "PCB_1X02_CONN_PCB_1_2_S_GMR_8_C".
    #8 Warning [ALG0016] Part Name "PCB_1X03_CONN_PCB_1_3_S_
    PCB_1X03_CONN_PCB_1_3_A_M, CONN_PCB_1_3_A_F" is renamed to "PCB_1X03_CONN_PCB_1_3_S_PCB_1X0".
    #9 Warning [ALG0016] Part Name "PCB_1X02_CONN_PCB_1_2_S_GMR_1_CONN_PCB_1_2_A_M, CONN_PCB_1_2_A_F" is renamed to "PCB_1X02_CONN_PCB_1_2_S_GMR_1_C".
    #10 Warning [ALG0016] Part Name "PCB_1X02_CONN_PCB_1_2_S_GMR_2_CONN_PCB_1_2_A_M, CONN_PCB_1_2_A_F" is renamed to "PCB_1X02_CONN_PCB_1_2_S_GMR_2_C".
    #11 Warning [ALG0016] Part Name "PCB_1X02_CONN_PCB_1_2_S_GMR_3_CONN_PCB_1_2_A_M, CONN_PCB_1_2_A_F" is renamed to "PCB_1X02_CONN_PCB_1_2_S_GMR_3_C".
    #12 Warning [ALG0016] Part Name "PCB_1X02_CONN_PCB_1_2_S_GMR_5_CONN_PCB_1_2_A_M, CONN_PCB_1_2_A_F" is renamed to "PCB_1X02_CONN_PCB_1_2_S_GMR_5_C".
    #13 Warning [ALG0016] Part Name "R_SMD_1206_1206_RES_REFLOW_820R_1206_1206_RES_WAVE" is renamed to "R_SMD_1206_1206_RES_REFLOW_820R".
    #14 Warning [ALG0016] Part Name "R_SMD_1206_1206_RES_REFLOW_4,7K_1206_1206_RES_WAVE" is renamed to "R_SMD_1206_1206_RES_REFLOW_4,7K".
    #15 Warning [ALG0016] Part Name "R_SMD_1206_1206_RES_REFLOW_0R_S
    MD_1206_RES_WAVE" is renamed to "R_SMD_1206_1206_RES_REFLOW_0R_S".
    #16 Warning [ALG0016] Part Name "R_SMD_1206_1206_RES_REFLOW_1K_1206_1206_RES_WAVE" is renamed to "R_SMD_1206_1206_RES_REFLOW_1K_1".
    #17 Warning [ALG0016] Part Name "R_SMD_1206_1206_RES_REFLOW_3,9K_1206_1206_RES_WAVE" is renamed to "R_SMD_1206_1206_RES_REFLOW_3,9K".
    #18 Warning [ALG0016] Part Name "R_SMD_1206_1206_RES_REFLOW_220R_1206_1206_RES_WAVE" is renamed to "R_SMD_1206_1206_RES_REFLOW_220R".
    #19 Warning [ALG0016] Part Name "R_SMD_1206_1206_RES_REFLOW_27R_1206_1206_RES_WAVE" is renamed to "R_SMD_1206_1206_RES_REFLOW_27R_".
    #20 Warning [ALG0016] Part Name "R_SMD_1206_1206_RES_REFLOW_680R_1206_1206_RES_WAVE" is renamed to "R_SMD_1206_1206_RES_REFLOW_680R".
    #21 Warning [ALG0016] Part Name "R_SMD_1206_1206_RES_REFLOW_680_1206_1206_RES_WAVE" is renamed to "R_SMD_1206_1206_RES_REFLOW_680_".
    #22 Warning [ALG0016] Part Name "INA128_DIP8_3_OBL_INA128_SOIC8_REFLOW" is renamed to "INA128_DIP8_3_OBL_INA128_SOIC8_".
    #23 Warning [ALG0016] Part N
    ame "TLV3502/SO8_SOIC8_REFLOW_TLV3502" is renamed to "TLV3502/SO8_SOIC8_REFLOW_TLV350".
    Scanning netlist files ...
    Loading... Y:\USER\S-WOLFC\SA\BOARDS\FPGA_INTERFACE\Signal_Aufnehmer\allegro/pstchip.dat
    Loading... Y:\USER\S-WOLFC\SA\BOARDS\FPGA_INTERFACE\Signal_Aufnehmer\allegro/pstchip.dat
    Loading... Y:\USER\S-WOLFC\SA\BOARDS\FPGA_INTERFACE\Signal_Aufnehmer\allegro/pstxprt.dat
    Loading... Y:\USER\S-WOLFC\SA\BOARDS\FPGA_INTERFACE\Signal_Aufnehmer\allegro/pstxnet.dat
    Error: Line 15 in file Y:\USER\S-WOLFC\SA\BOARDS\FPGA_INTERFACE\Signal_Aufnehmer\allegro/pstxnet.dat:
    	  Reference designators inconsistent in xprt and xnet files  
    	Detected in function: pstFindInstByOldPathName 
    Error: Line 15 in file Y:\USER\S-WOLFC\SA\BOARDS\FPGA_INTERFACE\Signal_Aufnehmer\allegro/pstxnet.dat:
    	  Error loading the net list file  
    	Detected in function: ddbLoadPstXFiles 
    #24 Error   [ALG0036] Unable to read logical netlist data.
    I found https://www.edaboard.com/thread33260.html where it is mentioned, that this is a problem of wrong names. They seems to be truncated and later cannot be found again (As far as I have understood).

    I found the truncated names in the *.dat files, but I do not understand how to avoid the truncation. In the property editor (opening by double clicking a device) I do not find those long names mentioned in the warnings.

    So my question is: What can I do to make things work?

    Thanks in advance
    Christian

    PS: If you need futher information, please feel free to ask.

    - - - Updated - - -

    Hello,

    after copying all sheets of the project in OrCAD Capture CIS into a bare, new project and rerunning the netlister, all went well. (A colleague told me this trick)

    Now the only question is: Why does this happen? And way to avoid copying all sheets?

    Thanks
    Christian

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  2. #2
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    Re: Errors in generating netlist in Cadence Capture CIS -> Allegro, what to do?

    https://www.edaboard.com/thread33260.html

    go through the link it will help you
    kapil



  3. #3
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    Re: Errors in generating netlist in Cadence Capture CIS -> Allegro, what to do?

    Quote Originally Posted by kabaleevisu View Post
    https://www.edaboard.com/thread33260.html

    go through the link it will help you
    As you might have overseen: I myself found the link (mentioned in my first message) but was not able to find the problematic strings in the parameter editor. If you could tell me some more information where to look, it would be very useful. Espacially I do not know where the "component name" is located. I think it is composed of different entries in the parameters but I do not knaow if that is correct.

    Thanks
    Christian



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  4. #4
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    Re: Errors in generating netlist in Cadence Capture CIS -> Allegro, what to do?

    You can open your pstxnet.dat file in som etext editor and check the line number 15 for the error.
    Also you can goto the "allegro" folder which is created in the directory where sch is saved and inthat look for netrev.lst file and open it in text editor you can get some idea from it that where exactly is the error.



  5. #5
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    Re: Errors in generating netlist in Cadence Capture CIS -> Allegro, what to do?

    try to open pstxnet.dat file using excel and check row 15 this net has some error you can rename it or correct the Error



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  6. #6
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    Re: Errors in generating netlist in Cadence Capture CIS -> Allegro, what to do?

    Hello,

    I have the 2 errors in netlist file. Please help me and tell me what to do. Thanks.


    ------ Oversights/Warnings/Errors ------


    ERROR: File "VD19.brd" is being edited by user "vpdo" on date "Wed Feb 11 12:45:34 2015" on system "WKS-47". Resolve lock file and re-run netrev.

    #1 ERROR(SPMHNI-175): Netrev error detected.

    #2 Run stopped because errors were detected

    netrev run on Feb 11 12:49:27 2015
    DESIGN NAME : 'QLNK-100001'
    PACKAGING ON Sep 10 2012 04:46:09

    COMPILE 'logic'
    CHECK_PIN_NAMES OFF
    CROSS_REFERENCE OFF
    FEEDBACK OFF
    INCREMENTAL OFF
    INTERFACE_TYPE PHYSICAL
    MAX_ERRORS 500
    MERGE_MINIMUM 5
    NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
    NET_NAME_LENGTH 24
    OVERSIGHTS ON
    REPLACE_CHECK OFF
    SINGLE_NODE_NETS ON
    SPLIT_MINIMUM 0
    SUPPRESS 20
    WARNINGS ON

    2 errors detected
    No oversight detected
    No warning detected
    ----------------------------------------------------------------------------------




  7. #7
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    Re: Errors in generating netlist in Cadence Capture CIS -> Allegro, what to do?

    your BRD file is locked or still being used by user "vpdo" get it unlocked then re-import the netlist.



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