What's the difference between behavioral and structural in vhdl?

I want to know about behavioral and structural description in vhdl. What are they and what's the difference between them?

thanks a lot.

Dear iVenky,

when you are modeling hardware, you can write code in different ways, independent on the HDL you are using (i.e., either VHDL or Verilog). Behavioral modeling refers to a way to write code (more precisely, to model your hardware design) based on its functionality: it's like writing the algorithm that solves your problem. With structural code, on the other hand, you are connecting different parts together to get the final design.

In some way you will generally use a mixture of the twos: if you think to bottom-up approach, you first create behavioral/algorithmic code for lowest-level blocks (e.g., flip-flop) and once you move up across the abstraction levels you mix different blocks together and connect them in a structural code (e.g., shift register). This is just a simplisitc overview, but gives you an insight on the difference.

Cheers

HDL text books are ususally distinguishing three different abstraction levels:
- structural (instantiating primitive entities, e.g. logic gates gates and flip-flops)
- dataflow (assignments using logic expressions)
- behavioral (if then, case statements etc.)

these are types of modelling..
i.e. the way of implementing the code..

in Structural modelling refers to that type of modelling in which we simply interconnect the components by mapping there ports by seeing the rtl diagram whereas
Behavioral modelling uses sequential statement inside the process statement and in it we implement the logic directly..and this modelling is preferred and is the highest level of abstraction

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these are types of modelling..
i.e. the way of implementing the code..

Structural modelling refers to that type of modelling in which we simply interconnect the components by mapping there ports by seeing the rtl diagram whereas
Behavioral modelling uses sequential statement inside the process statement ,in it we implement the logic directly and this modelling is preferred and is the highest level of abstraction.