Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Not all 'wire's and 'reg's shown in Verilog simulation

Status
Not open for further replies.
S

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
I'm using modelsim 6.5 to simulate a mixed language VHDL/Verilog design.
The VHDL section works well - However, not all Verilog 'reg's and 'wire's are added to the waveform view.

Any idea why ?
 

shaiko said:
I'm using modelsim 6.5 to simulate a mixed language VHDL/Verilog design.
The VHDL section works well - However, not all Verilog 'reg's and 'wire's are added to the waveform view.

Any idea why ?
Click to expand...

I know that for certain simulators, only the regs and wires of the top-level module will display in the simulation. So if your verilog module is not the top-level module, then its inputs and outputs will not be displayed in the simulation. That being said, I have never used modelsim; I do know that this is the case with other simulators, such as Lattice's Active-HDL.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
willissilliw,
case solved. The simulation window had a box that says: "optimize"
It was checked by default. As soon as I removed it - all regs and wire appeared.

If it was me - I would change "optimize" to : "make me wonder what's wrong with the sim for an hour"
 

shaiko said:
willissilliw,
case solved. The simulation window had a box that says: "optimize"
It was checked by default. As soon as I removed it - all regs and wire appeared.

If it was me - I would change "optimize" to : "make me wonder what's wrong with the sim for an hour"
Click to expand...

Glad to hear you solved your issue. Yes that is slightly confusing terminology.

Good luck...

-Willis
 

yes, and you can also use -voptargs=+acc with vsim. Not sure where it is in the GUI, but it keeps the visibility of all nets without removing other optimizations. Sims often take a long time, so removing all optimizations might not be practical in all cases.
 
  • Like
Reactions: shaiko

    S

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top