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Multiplication in vhdl

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Hello friends...

I wish to implement the following multiplication in vhdl

X = 20* (128 * A(7) + 64* A(6) + 32* A(5)+ 16* A(4) + 8 * A(3) + 4* A(2)+ 2* A(1) + A(0)

where x is an integer of range 0 to 5500
A is an array of 7 elements of integer type

the error which appears is

* cant have such operands in this context

plzzzz help
 

Library is missing. Which one is correct I don't remember but you should add IEEE.STD_LOGIC_UNSIGNED.ALL for unsigned numbers, or IEEE.STD_LOGIC_SIGNED.ALL for signed numbers. And also write down IEEE.NUMERIC_STD.ALL.

Your problem will be solved with library declerations but don't forget that 2 bits long and 5 bits long is equal 7 bits long number. Synthesizer may give an error about it.
 

Library is missing.
Click to expand...
Integer is a built-in type. Integer multiplication is always supported, although not necessarily synthesizable to hardware, depending on the synthesis tool.

It's not clear, which "context" the error message is referring to. But "=" isn't a legal VHDL assignment operator, it's a compare operator.
 

Thanks ILGAZ

I have tried using IEEE.NUMERIC_STD.ALL
but i get the same error.
is the size of x not proper
or should i use the keyword unsigned in front of the array element
X = 20* (128 * unsigned A(7) + 64* unsigned A(6) + 32* unsigned A(5)+ 16* unsigned A(4) + 8 * unsigned A(3) + 4* unsigned A(2)+ 2* unsigned A(1) + unsigned A(0)

i really don't know what change i have to make to remove this error

- - - Updated - - -

FvM I HAVE USED THE <= IN MY CODE

WHILE FRAMING MY QUESTION I HAVE USED = SIGN TO SHOW THE REAL EXPRESSION

CAN ANYBODY TELL WHICH DATA TYPE CAN BE USED WITH * OPERATOR
ALSO PLZZ TELL ME THT IF INTEGERS ARE ALLOWED
THEN WHY MY EXPRESSION IS GIVING THE ERROR * cant have such operands in this context
 

FvM I HAVE USED THE <= IN MY CODE

WHILE FRAMING MY QUESTION I HAVE USED = SIGN TO SHOW THE REAL EXPRESSION
Click to expand...
I wonder which other code details have been omitted in your post? It's effectively useless to discuss the problem this way.

Please show a full entity code, including signal/variable definitions that reproduces the error. You should also mention which simulation/synthesis tool you are using.
 

As FvM suggested, you shoul write down all your code.
You can use std_logic_vector type and you don't need any conversion.
Do all your work with std_logic type and declare libraries.
 

You can use std_logic_vector type and you don't need any conversion.
Click to expand...
In this case, the constants must get correct type and the expression bit length must be observed. It's changing the nature of the original integer expression.
 

FvM said:
In this case, the constants must get correct type and the expression bit length must be observed. It's changing the nature of the original integer expression.
Click to expand...

Sure you are right and I also mentioned it. When it is synthesized, I knew that it is converted to std_logic type by synthesizer. Am I right?
So, it may be the best way to choose std_logic at the beginning and consider its restrictions.
 

I would prefer ieee.numeric_std with signed or unsigned type to describe bit-accurate arithmetic. But also size constraint integer can work well for synthesis.

The original poster didn't mention the context of the expression or the purpose. At this point I won't bomb him with suggestions about coding styles.
 

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