engrMunna
Advanced Member level 4
Hi.
I am simulating a cmos ring oscillator at the schematic level. I want to simulate it with some "interconnect parasitic capacitance" at the output of each inverter. What do you think can be an approximate value of this capacitance that I need to put at the output of each inverter so that when I do the layout, there is not very much difference in the between the schematic and layout simulation results. I am working in UMC 180nm Tehcnology. Is 10femtoF a reasonable choice? Since this will be my first layout ever I don't know much about it. PLease help
I am simulating a cmos ring oscillator at the schematic level. I want to simulate it with some "interconnect parasitic capacitance" at the output of each inverter. What do you think can be an approximate value of this capacitance that I need to put at the output of each inverter so that when I do the layout, there is not very much difference in the between the schematic and layout simulation results. I am working in UMC 180nm Tehcnology. Is 10femtoF a reasonable choice? Since this will be my first layout ever I don't know much about it. PLease help