Help with verilog testbench for cic filter.

H.Hachem · Jul 22, 2012

Hey everyone,

I wrote a code for a cic filter using Verilog HDL. However, I do not know if my problem lies in the testbench I have written or in Multisim. I would appreciate it if someone could tell me if something is wrong in the following short test bench.

module test;
reg clk;
wire [7:0] x,y;
assign x=8'b 00000001;
wb_hp_f (.clk(clk),.x_in(x),.y_out

);
initial begin
clk=1'b0;
end
always
#1 clk=~clk;
endmodule

I simply want to start by testing the response to a series of ones. The code I used is the one in 'digital signal processing with FPGA' with minor modifications.

Thanks in advance

tariq786 · Jul 22, 2012

what is the problem right now? can you post the output or the error message?

H.Hachem · Jul 22, 2012

No error. its just everything is at constant 0 in Multisim and never changes!

tariq786 · Jul 23, 2012

remove
assign x=8'b 00000001;

and put
x = 8'b00000001;

inside initial block

and keep on changing it like
this

initial
begin
x = 8'b00000001;
#2;
x = 8'b00000010;
#2;
x = 8'b00000011;
#2;
x = 8'b00000100;
end

and let us know the result

tariq786 · Jul 23, 2012

remove
assign x=8'b 00000001;

and put
x = 8'b00000001;

inside initial block

and keep on changing it like
this

initial
begin
x = 8'b00000001;
#2;
x = 8'b00000010;
#2;
x = 8'b00000011;
#2;
x = 8'b00000100;
end

and let us know the result

sakthikumaran87 · Jul 23, 2012

declare 'x' as reg type and not as wire as it is an input to your testbench.

H.Hachem · Jul 23, 2012

Thanks for the replies. I managed to get it to work. It was a Modelsim problem, it was detecting my code as VHDL. Anyway, I'm facing another problem now. After running the test, the simulation does not get past i0 . Here is my code:

Code:

module cicdecim64 (x_in,y_out,clk);
input					clk;
input 	[7:0]		x_in;
output 	[7:0]		y_out;

parameter hold=0, sample=1;
reg					state; 	//sample or hold states
reg		[5:0]		count;	//count till 63 starting from 0
reg		[7:0]		x;			//input
wire		[23:0]	sx;		//sign extended input
reg		[23:0] 	i0;		//Integrator output section 0
reg 		[18:0]	i1;		//output section 1 under the consideration of Haugenauer's pruning
reg 		[13:0]	i2;
reg 		[11:0] 	i2d1, c1, c0; // Integrator+COMB 0
reg		[10:0] 	c1d1, c2;
reg 		[9:0] 	c2d1, c3;

always @(negedge clk)
begin : FSM  					// finite state machine
case (state)
hold : begin
if (count<63) 					// setting states for downsampling
state <= hold; 
else
state <=sample;
end
default :
state <= hold;
endcase
end

assign sx={{16{x[7]}},x_in};


// Integrator
always @(posedge clk)
begin: I							
x  <= x_in;
i0 <= i0+sx;
i1 <= i1+i0[23:7];
i2 <= i2+i1[18:5];
case (state) 					//downsample
sample : begin
c0 <= i2[13:1];
count <= 0;						//reset counter once a sample has been fetched
end
default :
count <= count+1;
endcase
end

// COMB
always @(posedge clk)
begin: COMB
i2d1 <= c0;						
c1   <= c0-i2d1;
c1d1 <= c1[11:1];				
c2   <= c1[11:1]-c1d1;
c2d1 <= c2[10:1];
c3   <= c2[10:1]-c2d1;
end

assign y_out=c3[9:2];
endmodule

Modelsim shows only clk , x_in , state, count, sx but everything else is constant red line. I guess the problem lies in ' i0 <= i0+sx ', since i0 is not predefined before this statement, modelsim is unable to calculate it. I tried predefining i0 but to no avail. Any ideas?

Thanks in advance.

sakthikumaran87 · Jul 23, 2012

Hi you havenot intialised any values using reset including your state. Try to change the logic of your coding

H.Hachem · Jul 23, 2012

Could you give me an example? I took the code from a book and modified the downsampling rate to suit my project

FvM · Jul 23, 2012

The Verilog standard specifies

The initialization value for reg, time, and integer data types shall be the unknown value, x.

If you don't implement an explicite reset signal, you have to supply initial values to make the simulation work.

H.Hachem · Jul 23, 2012

FvM said:
The Verilog standard specifies

If you don't implement an explicite reset signal, you have to supply initial values to make the simulation work.

Yes, that makes sense. I tried inserting the following after the declaration of ports and wires:

Code:

always @(posedge reset)
begin
i0<=24'd0;
i1<=19'd0;
i2<=14'd0;
end

while setting reset to jump from 0 to 1 at the beginning of the simulation. However, the compiler returns the following error:

Error (10028): Can't resolve multiple constant drivers for net "i0[23]" at wb_hp_f.v(45)

- - - Updated - - -

I used

Code:

initial begin
i0<=24'd0;
i1<=19'd0;
i2<=14'd0;
end

instead and got the code to compile. However, the problem with the simulation persists. Once a posedge clock is reached, we're back to the same point as before. :/

FvM · Jul 23, 2012

The reset action must be placed in the same always block driving the respective registers to avoid a multiple drivers error.

The initial block should generally work, but may be you have other signals that are undefined during the first clock edge. You can find out by thoroughly looking at the simulations results. It's just an everydays HDL simulation problem, a practioneer will solve in on the way without much thinking.

H.Hachem · Jul 26, 2012

I'm still struggling to get it to work. I only get the 1st output sample because of the initial values. However once the first positive clock edge occurs, the state of i0 changes to x and with it everything else. I tried changing the clock frequency but that did not help.

FvM · Jul 26, 2012

As said

you have other signals that are undefined during the first clock edge

This is the case at least for x. Why don't you trace the values of all involved variables in your simulation. That's waht simulation tools are made for.

H.Hachem · Jul 27, 2012

OK let's see here is my code now:

Code:

// cic decimation filter : R=64, M=1, N=3
module cicdecim64 (x_in,y_out,clk,reset);
input					clk,reset;
input 	[7:0]		x_in;
output 	[7:0]		y_out;

parameter hold=0, sample=1;
reg					state; 			//sample or hold states
reg		[5:0]		count;			//count till 63 starting from 0
reg		[7:0]		x;					//input
wire		[23:0]	sx;				//sign extended input
reg		[23:0] 	i0;		//Integrator output section 0
reg 		[18:0]	i1;		//output section 1 under the consideration of Haugenauer's pruning
reg 		[13:0]	i2;
reg 		[11:0] 	i2d1, c1, c0; // Integrator+COMB 0
reg		[10:0] 	c1d1, c2;
reg 		[9:0] 	c2d1, c3;



always @(negedge clk)
begin : FSM  					// finite state machine
case (state)
hold : begin
if (count<63) 					// setting states for downsampling
state <= hold; 
else
state <=sample;
end
default:
state <= hold;
endcase
end

assign sx={{16{x[7]}},x_in};


// Integrator
always @(posedge clk)begin
if(reset) begin
i0 <= 24'd0;
i1 <= 19'd0;
i2 <= 14'd0;
x  <= 8'd0;
end
else
x  <= x_in;	
i0 <= i0+sx;
i1 <= i1+i0[23:7];
i2 <= i2+i1[18:5];
case (state) 					//downsample
sample : begin
c0 <= i2[13:1];
count <= 0;						//reset counter once a sample has been fetched
end
default :
count <= count+1;
endcase
end

// COMB
always @(posedge clk)
begin: COMB
i2d1 <= c0;						
c1   <= c0-i2d1;
c1d1 <= c1[11:1];				
c2   <= c1[11:1]-c1d1;
c2d1 <= c2[10:1];
c3   <= c2[10:1]-c2d1;
end

assign y_out=c3[9:2];
endmodule

Test bench:

Code:

`timescale 1ns/1ps
module test;
reg				clk,reset;
reg	[7:0] 	x;
wire 	[7:0]		y;

cicdecim64 cic (x,y,clk,reset);
initial begin
x <=8'd1;
clk<=1'b0;
reset <= 1'b0;
#4 reset=~reset;
#5 reset=~reset;

end
always
#4 clk=~clk;

endmodule

Simulation :
**broken link removed**

As you can see reset is only resetting x and ignoring the others.

Earlier, I tried to follow your suggestion. Everything before i0 (including x and sx) was defined all the time. This means the problem lies in i0 <= i0+sx;

FvM · Jul 27, 2012

You have to care, that the reset is applied to all register signals at the same time. That's apparently not the case in your testbench.

If you use a synchronous reset, the reset signal must not be applied exactly at the clock edge, this causes a race condition.

ali kotb · Jun 29, 2013

hello,
I have the same problem, I am new to DSP and verilog.
I am an analog designer and I need CIC filter for sigma delta ADC,
can u help me with the test bench code , I used Meyer code for DUT with some modifications

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