H.Hachem
Junior Member level 3
Hey everyone,
I wrote a code for a cic filter using Verilog HDL. However, I do not know if my problem lies in the testbench I have written or in Multisim. I would appreciate it if someone could tell me if something is wrong in the following short test bench.
module test;
reg clk;
wire [7:0] x,y;
assign x=8'b 00000001;
wb_hp_f (.clk(clk),.x_in(x),.y_out);
initial begin
clk=1'b0;
end
always
#1 clk=~clk;
endmodule
I simply want to start by testing the response to a series of ones. The code I used is the one in 'digital signal processing with FPGA' with minor modifications.
Thanks in advance
I wrote a code for a cic filter using Verilog HDL. However, I do not know if my problem lies in the testbench I have written or in Multisim. I would appreciate it if someone could tell me if something is wrong in the following short test bench.
module test;
reg clk;
wire [7:0] x,y;
assign x=8'b 00000001;
wb_hp_f (.clk(clk),.x_in(x),.y_out);
initial begin
clk=1'b0;
end
always
#1 clk=~clk;
endmodule
I simply want to start by testing the response to a series of ones. The code I used is the one in 'digital signal processing with FPGA' with minor modifications.
Thanks in advance