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Why is test bench required if we can get outputs from individual modules?

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kunalec3

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why does a test bench is required if we can get the outputs from individual modules....... where do we add the test bench in the package or in the main module

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can i get the codes for top module of the individual modules of aes 128 bit algorithm.............. i am in great need of help i am attaching the copy of individual modules.... plz some one help me...this link shall provide u with the individual modules in the thesis........www.ece.unm.edu/~jimp/HOST/DES_AES_VHDL/AESvhdl.pdf
 

Re: query for test bench

testbenches are used in simulators and not synthesisors. They are for testing purposes only.
 

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